7 October · FPGA PCB and LDO update

Major updates on 10/7

1. FPGA PCB update

Material list complete. Finalizing schematic and layout; routing has not started.

2. Alternative method: LDO → XEM8305 module

Working on schematic and routing; confirming dimensions.

Sources: Howard’s 7 October meeting-update wording. Current M1 and received carrier native sources. Files and provenance

01 / 08

Zitong’s complete component list

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Sources: Zitong_1007_Original.pptx, complete slide 1. Files and provenance

Zitong’s entire original slide is preserved without rewriting or cropping: FPGA and package, LEDs, reference clock, flash, inventory statements, comparison parts and the source boot-validation caveat. Inventory figures are dated source statements. Pan and zoom to discuss individual entries. Zitong's source calls XC7A35T-2CSG325I the final FPGA decision. Its requirements are XC7A series, at least two GTP lanes, more than 120 user I/Os, more than 100 units in stock, authorized AMD distributors and the smallest suitable package. It reports 122 units at JLCPCB and says packages smaller than 15 × 15 mm do not provide enough I/Os for this design. These are Zitong's dated selection claims, rather than current purchasing verification. M1 retains this FPGA and both indicators. The eight-chip statement describes the intended system, rather than demonstrated operation. This slide preserves Zitong's proposed clock list and order. The source says Jiaao confirmed that one oscillator can serve the FPGA and GTP clock domains. The oscillator is described as 3.2 × 2.5 mm, ±25 ppm and 186 fs RMS phase jitter typical. The splitter is described as 1:2 LVDS, 1.8 V, up to 2 GHz and VQFN-16 at 3 × 3 mm. Review comments belong here: the source asks for better than ±20 ppm while listing ±25 ppm, and RMS phase jitter does not establish its <10 ps peak-to-peak cycle-to-cycle jitter request. The reported oscillator characterization uses 3.3 V rather than M1's selected 1.8 V. The typed LMK1D2102LRGTR suffix differs from the source's linked LMK1D2102RGTR. M1 adopts the oscillator and AC coupling, but provisionally omits the LMK while the GTP ODIV2 fabric-clock route awaits Vivado verification. Listing the LMK here records Zitong's proposal, rather than claiming it is fitted in M1. This slide preserves Zitong's flash section and programming workflow. Its requirements are small size, a single SPI interface, Vivado recognition and Artix-7 support. The source gives the ISSI flash a 1.65–1.95 V supply and up to 166 MHz operation. It gives the NXP translator 1.08–1.95 V A-side, 1.65–3.6 V B-side, up to 208 MHz and XQFN-16 at 2.6 × 1.8 mm. Reported inventory and future distributor arrival dates are dated source claims and stay out of the slide body. The source explicitly says NVT4858 was designed for SD/SDIO and that FPGA boot/configuration behavior still needs validation. M1 adopts these exact parts with SPI x1, adapted idle biases and separate boot holds. Physical boot and brownout behavior remain open. The displayed programming path is the source's intended workflow, rather than a completed software demonstration.

02 / 08

FPGA PCB schematic

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Sources: FPGA35T_M1.kicad_sch and ASIC_Signals.kicad_sch, native KiCad SVG exports. Files and provenance

Native M1 two-sheet schematic, unchanged. Select either sheet, then pan and zoom. Gerald’s guidance is to match related clock/data, review bypass, returns and manufacturable escapes. This is a schematic-checked direct-interface prototype; routing, clock implementation, sequencing and hardware validation remain open. The October 6 feedback highlighted routing quality, regular placement and unmatched delays. The earlier directions also call for power-distribution checks, practical blind-via escapes, compact placement and bottom connectors. Our engineering application is to review the full signal and return path, not only visual symmetry. A factory stackup and guaranteed ASIC timing still need evidence. Our next concrete review should use the native two-sheet FPGA drawing and the new carrier PCB. The requirements that still need ASIC-side evidence are pad levels, recording data-valid timing, rail currents and power-loss behavior. The fabrication stackup and mechanical seating need supplier or physical evidence. The one-chip XEM path is the first integration step, with eight-chip scaling following verified results.

03 / 08

FPGA PCB layout · KiCad and 3D

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Open 3D to rotate the native model.

41 × 41 mm · layout in progress · routing has not started.

Sources: FPGA35T_M1.kicad_pcb. M1 native validation and snapshot manifest. M1 native 3D export. M1 3D model provenance. Files and provenance

The board size stays at 41 by 41 millimeters. We have removed parts and regrouped clock and flash support, but freed placement space does not automatically make the board smaller. The four floating mezzanine connectors remain on the bottom. This is the actual M1 PCB, with expected unrouted connections. The earlier README lists 40 × 40 mm, but fresh native centerline geometry measures 41 × 41 mm. Use the measured outline here. The CLI lists only 499 of the 1,091 actual pending PCB connections. Rotate the model to show the component side and the four bottom connector locations. The geometry comes from the native PCB. Some bodies are explicitly labeled nominal envelopes, including the new oscillator and translator. This model supports review of placement and side, but cannot establish a populated fit result. Pan/zoom the actual native SVG; rotate or zoom the actual native model independently.

04 / 08

XEM8305, carrier and LDO

XEM8305 on the carrier with the existing LDO connected below

Open 3D to rotate the native model.

Nominal assembly; dimensions and connector fit under review.

Sources: Board_Howard native carrier. Original LDO native PCB. Official Opal Kelly XEM8305 mechanical model. https://www.opalkelly.com/products/models/. https://docs.opalkelly.com/xem8305/expansion-connectors/. Files and provenance

05 / 08

Existing ASIC LDO board

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Open 3D to rotate the native model.

Existing LDO design; fitted rails and connector fit under review.

Sources: Original LDO native PCB and schematic. Native KiCad layout and 3D exports. Files and provenance

Show the LDO and carrier sides of each connector pair. J1 provides the defined LDO circuit interface. J19 remains a required physical mating point even though its source contacts are electrically unassigned. The native pad positions register in plan; final connector seating and board clearance are still to be confirmed against populated hardware and supplier mechanical data. The original J19 has 24 signal-pad positions and four additional numbered end pads. The end-pad function and numbering remain to be confirmed; 28 CAD pads should not be described as 28 electrical connector contacts. This is Gerald’s existing LDO design. Its 23 digital signals pass directly between the connectors. The rail intents include separate nominal 1.5 V domains, 1.6 V, 0.75 V and two high-stage circuits. The high-stage sign and reference must stay explicit. All nine LDO power-good outputs are unused in the saved circuit, so a raw-input monitor does not establish that every ASIC rail is ready. Actual fitted parts, currents, return bonding and power order remain to be checked. The new Desktop package contains the connector-foundation carrier. Show where the LDO and XEM sockets sit and how the recording bus runs between them. Do not call this a complete powered carrier. The older R3 and R5 circuits remain different revisions, and the R3 manufacturing hold remains in place. The received board uses two copper layers and has no ground plane. The saved Step 8 uses four copper layers and a dedicated In1.Cu DGND plane. Select top, underside, J1 or J19 on the left. Select the carrier or LDO 3D on the right. Source generic bodies and missing connector housings do not qualify physical seating.

06 / 08

Current carrier PCB · KiCad and schematic

Drag to pan · scroll to zoom

Drag to pan · scroll to zoom

Carrier layout, schematic and routing in progress.

Sources: Received Board_Howard native PCB and schematic. Native KiCad SVG exports. Files and provenance

These are the actual received carrier connector-foundation schematic and original LDO schematic. The carrier has five connector symbols and 23 direct signal mappings; its power/startup circuit is not complete. The LDO source has nine LT3042 stages. J19 is mechanically present on the PCB but has no schematic symbol or assigned source nets. This is Gerald’s existing LDO design. Its 23 digital signals pass directly between the connectors. The rail intents include separate nominal 1.5 V domains, 1.6 V, 0.75 V and two high-stage circuits. The high-stage sign and reference must stay explicit. All nine LDO power-good outputs are unused in the saved circuit, so a raw-input monitor does not establish that every ASIC rail is ready. Actual fitted parts, currents, return bonding and power order remain to be checked. The new Desktop package contains the connector-foundation carrier. Show where the LDO and XEM sockets sit and how the recording bus runs between them. Do not call this a complete powered carrier. The older R3 and R5 circuits remain different revisions, and the R3 manufacturing hold remains in place. The received board uses two copper layers and has no ground plane. The saved Step 8 uses four copper layers and a dedicated In1.Cu DGND plane. Show the LDO and carrier sides of each connector pair. J1 provides the defined LDO circuit interface. J19 remains a required physical mating point even though its source contacts are electrically unassigned. The native pad positions register in plan; final connector seating and board clearance are still to be confirmed against populated hardware and supplier mechanical data. The original J19 has 24 signal-pad positions and four additional numbered end pads. The end-pad function and numbering remain to be confirmed; 28 CAD pads should not be described as 28 electrical connector contacts. This is Gerald’s existing LDO design. Its 23 digital signals pass directly between the connectors. The rail intents include separate nominal 1.5 V domains, 1.6 V, 0.75 V and two high-stage circuits. The high-stage sign and reference must stay explicit. All nine LDO power-good outputs are unused in the saved circuit, so a raw-input monitor does not establish that every ASIC rail is ready. Actual fitted parts, currents, return bonding and power order remain to be checked. The new Desktop package contains the connector-foundation carrier. Show where the LDO and XEM sockets sit and how the recording bus runs between them. Do not call this a complete powered carrier. The older R3 and R5 circuits remain different revisions, and the R3 manufacturing hold remains in place. The received board uses two copper layers and has no ground plane. The saved Step 8 uses four copper layers and a dedicated In1.Cu DGND plane. Select top, underside, J1 or J19 on the left. Select the carrier or LDO 3D on the right. Source generic bodies and missing connector housings do not qualify physical seating.

07 / 08

Moving forward

1. Confirm and complete the FPGA PCB schematic.

2. Begin routing the FPGA PCB.

3. Confirm the carrier board layout, schematic and routing.

Sources: Howard’s requested final-slide wording, 7 October 2026. Files and provenance

08 / 08

Major updates on 10/7

1. FPGA PCB update

2. Alternative method: LDO → XEM8305 module

Zitong’s complete component list

FPGA PCB schematic

FPGA PCB layout · KiCad and 3D

XEM8305, carrier and LDO

Existing ASIC LDO board

Current carrier PCB · KiCad and schematic

Moving forward

Meeting files and native projects

Rotate the original LDO board

Zitong’s original slide