{
  "date_local": "2026-10-07",
  "timezone": "America/Chicago",
  "kind": "weekly design-review presentation",
  "source_facts": [
    {
      "id": "zitong",
      "origin": "Desktop/Zitong_1007 (1).pptx",
      "date": "2026-10-07",
      "sha256": "2b967d58cbe929603f64835da169a6c8073ae7bfeaf4f4ae2ef93072a76a710d",
      "status": "original one-slide proposal, unchanged copy"
    },
    {
      "id": "M1",
      "origin": "2026-10-06_FPGA_Work/09_R39_Minimum_Buffer_Candidate/project/hardware/FPGA35T_M1.kicad_pro",
      "pcb_sha256": "0039db6a96a444cd4a2315a2883ea5c7e149ceb3efe1ade66d0baac317913e3b",
      "size_mm": [
        41,
        41
      ],
      "footprints": 287,
      "tracks": 0,
      "vias": 0,
      "planes": 0,
      "unrouted_connections": 1091,
      "date_checked": "2026-10-07",
      "checks": {
        "ERC_delivered_settings": 0,
        "physical_DRC": 0,
        "parity": 0
      },
      "status": "unrouted prototype/review, physical qualification open"
    },
    {
      "id": "R39",
      "origin": "2026-10-05_FPGA_Work/02_R39_Engineering_Closure/project/hardware/FPGA35T_V15.kicad_pro",
      "pcb_sha256": "24fee50ce9d4716d141ff1ef69a9f5ebf692b9ca4f0834c81ed87eed4ed629b9",
      "size_mm": [
        41,
        41
      ],
      "footprints": 343,
      "tracks": 113,
      "vias": 0,
      "planes": 0,
      "unrouted_connections": 1413,
      "date_checked": "2026-10-07",
      "checks": {
        "ERC_delivered_settings": 0,
        "physical_DRC": 0,
        "parity": 0
      },
      "status": "unrouted prototype/review, physical qualification open"
    },
    {
      "id": "desktop_board_howard",
      "origin": "Desktop/Board_Howard",
      "pcb_sha256": "9b28824b1acb05182390577897a62f5ce9644f66c6a72cb872183e7076a5043f",
      "copper_layers": 2,
      "footprints": 5,
      "tracks": 140,
      "vias": 19,
      "zones": 0,
      "status": "received draft with unconfirmed authorship"
    },
    {
      "id": "step8_carrier",
      "origin": "6 October applied Step 8",
      "pcb_sha256": "642f53f10c2822b20b868a49569ac71dff1f161765ec60bf41b4f2a84618397b",
      "copper_layers": 4,
      "footprints": 5,
      "tracks": 242,
      "vias": 105,
      "zones": 1,
      "status": "separate baseline/reference with qualification open"
    },
    {
      "id": "original_ldo",
      "origin": "2 October supplied original Gerald LDO",
      "pcb_sha256": "74ed99fa1a91cc73ad9b93946fd1b386a5a99355ad15efb51276b0db660e3425",
      "copper_layers": 6,
      "footprints": 80,
      "tracks": 933,
      "vias": 292,
      "zones": 78,
      "status": "separate baseline/reference with qualification open"
    },
    {
      "id": "gerald-guidance",
      "origin": "Howard’s saved relayed directions, 4 and 6 October",
      "status": "recorded advice and engineering application, not a verbatim new message or silicon/factory specification"
    }
  ],
  "native_checks_received_carrier": {
    "errors": 38,
    "dangling_track_warnings": 21,
    "assigned_unconnected_items": 20,
    "parity_warnings": 204
  },
  "native_checks_step8": {
    "physical_DRC_findings": 0,
    "assigned_unconnected_items": 0,
    "parity_warnings": 204,
    "unassigned_contacts": 234
  },
  "geometry_limits": [
    "M1 outline is 41 × 41 mm from Edge.Cuts centerlines; the older README 40 × 40 mm claim is stale.",
    "M1 contains nominal AX3/NVT and inherited model envelopes; 28 test/jumper footprints lack body models.",
    "Original LDO render includes generic source header bodies; installed population is unverified.",
    "The original standalone carrier/LDO source exports omit Hirose J1/J19 housings. The new assembly study adds separately documented model geometry and nominal seating; it does not qualify a populated fit.",
    "The assembly uses the received two-layer Desktop carrier, not the separate four-layer Step 8 baseline. Original electrical PCB source files are retained."
  ],
  "derivation": "Zitong’s complete original slide is retained without cropping. Native KiCad SVG drawings support browser pan and zoom. Native GLB models support rotation and zoom. The assembly uses nominal mating positions with preserved source geometry. PowerPoint/PDF contain static overview views. Howard’s exact eight-slide order and three next steps are used.",
  "packaging": "Native PCB/SCH/PRO bytes preserved. Public README replaced for corrected measured size and privacy. Local library lookup repaired in carrier/LDO snapshots. Hidden histories/cache/settings, private chat/audio and manufacturing outputs omitted.",
  "published_files": [
    {
      "path": "presentation/meetings/assets/2026-10-07/Zitong_Original_Slide_1.png",
      "bytes": 291850,
      "sha256": "d2c19c72075aae96c8325074428b14e92309606a289da01e42efb6d640bc5c96"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/assembly/Assembly.glb",
      "bytes": 34856268,
      "sha256": "5d161e3b674dd9c28771b4c3911ea51b299e0984eee1ce477e2d88e240c76284"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/assembly/Assembly_3D.png",
      "bytes": 88435,
      "sha256": "d3627039fae432f5b815e3b123897f2a91c3d5de94b9a1a43fb1deb78d4d1263"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/assembly/J19_Closeup.png",
      "bytes": 30304,
      "sha256": "77f714ce6ecd3cd443e22ced5c10cad22adc1b0b6eea91e07ab64c5b378c7975"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/assembly/J1_Closeup.png",
      "bytes": 38343,
      "sha256": "d5a351a8da37ea50d2fcbb5734eeca0b055530e51130bfe54096b6623f05d34f"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/fpga/M1.glb",
      "bytes": 15273852,
      "sha256": "d3c6a505cb9a320c96a71ea8ff51763d2f06678aa8f4d1250089a8b9ef9270dc"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/fpga/M1_3D.png",
      "bytes": 1462294,
      "sha256": "eb4a4a0f6a3788a0ddd155740d0bb0a9318629d275352d105cc46b286f73e1ee"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/fpga/M1_Bottom.png",
      "bytes": 618851,
      "sha256": "f94f23d8ee8205679a73f08fb861f9f7a451464ab4068bfa0c47f95946e07078"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/fpga/M1_Top.png",
      "bytes": 606074,
      "sha256": "2a9d7caa942d438a688fc5122baf41b8fb6af0d2d14efd3422b8cba37af69610"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/assembly/Assembly_Connected_3D.png",
      "bytes": 8334,
      "sha256": "60f7005e7d594ee4b343aef0955715dda5e7da932462d6890b293e6c889c65f2"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_3D.png",
      "bytes": 1462294,
      "sha256": "eb4a4a0f6a3788a0ddd155740d0bb0a9318629d275352d105cc46b286f73e1ee"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_PCB_Bottom.png",
      "bytes": 293851,
      "sha256": "62f0fc4d8be3fd9919005be5db04ed178afb683ce0ce59b9a1459493b1ba2655"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_PCB_Bottom.svg",
      "bytes": 203838,
      "sha256": "3eb4c9a4307db0ec3922ecf6be56ab8a3fe1f1c01d9237d4f3b0c031843ab47c"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_PCB_Top.png",
      "bytes": 327116,
      "sha256": "7af8f9988cf5dd0cd6bfd0fba5333f8193185618d951153b2d798ba7902f0899"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_PCB_Top.svg",
      "bytes": 171699,
      "sha256": "31a46423e2e9a89b1f2da004efeea9bb7beecd3c4429ae1c59d8f3aa50f1abe1"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_Schematic_ASIC_Signals.png",
      "bytes": 409853,
      "sha256": "eec2472ca5aee6aff3ed61e2531be8641a7df748024135e65d6caa788f218db0"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_Schematic_ASIC_Signals.svg",
      "bytes": 6672248,
      "sha256": "e54b3f5d78aaf0e72ca6b644846de037ae4c27148ec13ebd8bfb2e386fef496f"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_Schematic_Main.png",
      "bytes": 415280,
      "sha256": "deb22f70aca0fc2dd4d5f48b78e0491eee62d9b98119a576cf834df99f717370"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/fpga/M1_Schematic_Main.svg",
      "bytes": 7457856,
      "sha256": "90689c85975e550f952d0d3d40708bdfea78e47ef1205629c5264886d74f37fb"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/Carrier_Bottom.svg",
      "bytes": 40585,
      "sha256": "0c443bc20b5b198972c23dc00462a6168f53bf01dfacc3cb2f5e189879b56e55"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/Carrier_Schematic.png",
      "bytes": 830927,
      "sha256": "2b0bb26dd3dbac3deb76d86bb8514bbe1ab0c6bf0f4b34b058a35b5595dad71a"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/Carrier_Schematic.svg",
      "bytes": 3722897,
      "sha256": "1aaf31a04cdd9cf2437ee967bc4b805ddaa6a948dc211291648785bd730ea4b7"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/Carrier_Schematic_Preview.png",
      "bytes": 832552,
      "sha256": "023a3218088b3872b1f034aa5aa3d484a5b2aaf4693bfd8d0b0137e104d74c86"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/Carrier_Schematic_White_Preview.png",
      "bytes": 830927,
      "sha256": "2b0bb26dd3dbac3deb76d86bb8514bbe1ab0c6bf0f4b34b058a35b5595dad71a"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/Carrier_Top.svg",
      "bytes": 54052,
      "sha256": "7aae6d97cb81bc631d6df8ce6dbe8cf1b688058908bdd419d9d17e71c1e2d9af"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/LDO_Bottom.svg",
      "bytes": 227792,
      "sha256": "90a4b81e66a232c7a4795e4693cf64e45a1f29a75b2504321b288e62acf94575"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/LDO_Schematic.png",
      "bytes": 366293,
      "sha256": "316745e3f040f0a33da605d3c7c4475e621f12ffac7f6afc440a83ec719c61fa"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/LDO_Schematic.svg",
      "bytes": 1063250,
      "sha256": "deff183460c6ff9314f3802445e15d4a41160e624d46ccfd3be97af97c777ffc"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/LDO_Schematic_Preview.png",
      "bytes": 363119,
      "sha256": "1d2d00623d649fb931327c96914511dbf42689d7ce74000ac78f1d4dc9c0d533"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/LDO_Schematic_White_Preview.png",
      "bytes": 366293,
      "sha256": "316745e3f040f0a33da605d3c7c4475e621f12ffac7f6afc440a83ec719c61fa"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/interactive/ldo/LDO_Top.svg",
      "bytes": 280398,
      "sha256": "27a7a95396417bc81b9efa95880bd95ffe67af5b49d17ac289f73f0396ee4745"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/ldo/Carrier.glb",
      "bytes": 8048264,
      "sha256": "767cd201deaeb8a6ed54d1e507fbc10dab16cf4c88f16b0154c8c1f46686079a"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/ldo/Carrier_3D.png",
      "bytes": 805421,
      "sha256": "6ad6116ba9772bdb34a07ac31a81c23b8866e4daa9df2c0a3ce80e7ab2bc005d"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/ldo/Carrier_Bottom.png",
      "bytes": 43446,
      "sha256": "77a7df9db0a89421e63e663e77ab07579a64fdc9171ad776d5252b6bfc2d8cbc"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/ldo/Carrier_Top.png",
      "bytes": 62256,
      "sha256": "a864ecc1d06ba37f157bacbd9b7cb3ea99c02f575f5b09f1c98791845c9a6fe3"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/ldo/LDO.glb",
      "bytes": 14499732,
      "sha256": "2f7369dab38ded1e934b2d3ebbc8b6a8cc7478379717b7ec15698c328d79d3e8"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/ldo/LDO_3D.png",
      "bytes": 820648,
      "sha256": "10ba778c81440dc1897d92e21ec761e33320f9eeec890eb9811efc8be8be1620"
    },
    {
      "path": "presentation/meetings/assets/2026-10-07/ldo/LDO_Top.png",
      "bytes": 558278,
      "sha256": "84e65229b32cee7c8afc451d3ec453ff474fc32e8c25e758e5abe177b42e6cc1"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Assembly_Visual_Provenance.json",
      "bytes": 23348,
      "sha256": "82bd20804aabc3c9fe3f008bab43b39d6dbae15a59eb97e5a90c776705e6fa84"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Assembly_Visual_Study_KiCad.zip",
      "bytes": 20423825,
      "sha256": "838b0e178fca4a34429baec9dc7f9b008af04a52db356152c620e5f6632f54d0"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Board_Howard_KiCad.zip",
      "bytes": 1953160,
      "sha256": "222bfb335b3a97d09860ace28fa4d5bdc62deb13efeada0e52182c940f1a20d3"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Carrier_Step8_KiCad.zip",
      "bytes": 1973499,
      "sha256": "8070d00435f9a76355c1cf7a9f9f3c346615c15d7ab444eeb40a82d83f926d40"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/FPGA35T_M1_KiCad.zip",
      "bytes": 2718076,
      "sha256": "ca6da736216199915be67c0cc18469594479589712d0df087286ca5b63af4b3c"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/FPGA35T_M1_Two_Sheet.pdf",
      "bytes": 1165049,
      "sha256": "a0027f7c76225acc83671abf3dfa2207898f800e40320e5e2ee4187637ea9682"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/LDO_Original_KiCad.zip",
      "bytes": 427306,
      "sha256": "0839860d632ce50777e022a59a4e7aceb5ffa864252a4cde6adfa2b98248bc93"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Meeting_Review_2026-10-07.md",
      "bytes": 5482,
      "sha256": "0c8cf0a61673c1282a9897f5bff53772212a6ee243449d1b0413216c5ab3dd4b"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Native_Interactive_Provenance.json",
      "bytes": 42721,
      "sha256": "c65c162a0338baa428024317337a70e67885adfcd7151179770e1ee6bf74eec3"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Slide_Content_2026-10-07.json",
      "bytes": 16628,
      "sha256": "dd82ae43f819e325953388a048130c891f7092ca050ff48a6f83907c3b90c447"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Weekly_FPGA_LDO_Update_2026-10-07.pdf",
      "bytes": 3855023,
      "sha256": "33723d1ed79ea6f931a63d22a70ef917b71a4c435cf6a276de572c834b648aa3"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Weekly_FPGA_LDO_Update_2026-10-07.pptx",
      "bytes": 5046547,
      "sha256": "c0cc69cdfd0a428aa1e38b05ec627c0ec824fc8be81511dc248bba7f71d4b925"
    },
    {
      "path": "presentation/meetings/files/2026-10-07/Zitong_1007_Original.pptx",
      "bytes": 97898,
      "sha256": "2b967d58cbe929603f64835da169a6c8073ae7bfeaf4f4ae2ef93072a76a710d"
    }
  ],
  "presentation_revision": "R4 Howard’s requested eight-slide order",
  "slide_count": 8,
  "assembly_visual_provenance": "Assembly_Visual_Provenance.json",
  "native_interactive_provenance": "Native_Interactive_Provenance.json",
  "requested_delivery_formats": [
    "HTML"
  ]
}
