Checked files
Native ERC, DRC, unrouted items and schematic/PCB parity are all zero. The Gerber/drill export passes 144 checks, and actual paste/mask/outline geometry passes 766 checks. No CAD checks are ignored or excluded.
Current carrier · R12 · 9 October: Open the current six-layer carrier and complete component 3D views. The page below is a preserved earlier revision.
Direct LDO → carrier → XEM8305
XEM8305 direct carrier R3
Prototype files · factory and assembly review pendingThe existing LDO plugs into this carrier, which plugs directly into XEM8305. One design includes all three XEM sockets, onboard 2.5 V / 3.3 V supplies from an external 12 V input, and the switched ASIC interface.
6 layers · 53 × 83 mm carrier73 × 83 mm handling panel260 XEM contacts accounted for8 schematic sheetsNative ERC / DRC / opens / parity: 0
Download all filesKiCad ZIP, schematic, 3D model, board views, Gerbers and check summary.
Gerber + drill ZIPSix-layer prototype PCB files, outline/V-cuts and fabrication instructions.
Editable KiCad projectPCB, all eight schematic sheets, project settings and local libraries.
Complete schematic PDFEight sheets matching the R3 circuit; print layout reviewed.
File sizes and checksums · Checks and remaining qualifications
Rotate the carrier
Open the 3D view to rotate the carrier.
Drag to rotate · scroll to zoom · right-drag to pan
Actual native carrier board, pads and outer copper, with project-authored nominal component envelopes. The envelopes show position and side; exact manufacturer housings and the assembled XEM/LDO stack are omitted. This view does not qualify physical fit. Geometry receipt · Download 3D model.
KiCad board views
Native exports from the checked R3 board. View all six exported copper layers and handling rails.
Complete circuit
Eight-sheet schematic
Open the complete PDF or use the embedded preview. The editable sheets are included in the KiCad ZIP. For readability, the PDF uses a documented print-layout copy; component and net topology are identical. Print-layout notes.
Manufacturing status
Local checks pass; factory review remains
Before an assembled order
JLCPCB must accept the fine connector/IC lands, filled vias, handling panel and soldering process. Exact component sourcing and placement orientation still need review. No factory approval or order has been obtained.
Prototype construction
Six-layer FR-4, 1.6 mm, JLC06161H-3313 stack, 1 oz outer / 0.5 oz inner copper, green mask, white legend and ENIG. Specify epoxy-filled/capped all Ø0.30 mm vias. The two marked lines are V-cuts; remove the side rails after assembly. Follow the instructions inside the Gerber ZIP.
First-board acceptance
Check simultaneous connector seating, actual loads, startup and temperatures before attaching the ASIC. R5 ARM starts DNP/off. Aggregate VCCO commissioning is limited to 50 mA pending measured bank voltages. ASIC timing, firmware and powered operation remain unqualified.
Interface details
All three XEM sockets are accounted for
MC1 has 100 contacts; MC2 and MC3 each have 80. MC3 connects 28 ground contacts and reserves 52 explicit no-connects. J1 carries the mapped ASIC interface and named rails; J19 is a mechanical mating pair with its contacts explicitly NC. CLKH is supplied from FPGA to ASIC, while CLK32MHZ returns from ASIC to FPGA for capture.
J3 is the external 12 V input. J4/J5 are generated-rail test points. The existing LDO’s stimulation supplies and analog-ground contract remain separate. Signal-isolation and rail-supervision circuits are implemented in the R3 schematic; their actual assembled behavior still needs testing.
Preserved revisions
Earlier reviews
Direct R2 · preserved four-layer reviewA1R2 cabled assemblyE5 cabled adapterSeparate 35T R39 project
These earlier files retain their own revisions and checks. R3 publication does not approve fabrication, assembly or system operation.