{
  "revision": "R2 assembly first, with major updates on page 2",
  "kind": "Native CAD visualization study. Nominal seating and fit remain unverified.",
  "study": {
    "kind": "visualization-only model study, not electrically altered or fabrication qualified",
    "source_pcb": "XEM8305_LDO_Carrier_Connector_Foundation.kicad_pcb",
    "source_sha256": "9b28824b1acb05182390577897a62f5ce9644f66c6a72cb872183e7076a5043f",
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    "assembled_pcb": "XEM8305_LDO_Carrier_Connector_Foundation.kicad_pcb",
    "exploded_pcb": "Assembly_Exploded_Visual_Only.kicad_pcb",
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      "LDO_native_transform": "x=source_x-52.3; y=84.2-source_y; z=-source_z-2; LDO flipped about X",
      "J1_planar_center_residual_mm": 0,
      "J19_planar_center_residual_mm": 0,
      "XEM_native_transform": "x=vendor_v+101; y=vendor_u+26; z=vendor_z+8.2",
      "nominal_module_mating_gap_mm": 5,
      "nominal_ldo_mating_gap_mm": 2,
      "exploded_visual_added_spacing_mm": 35,
      "module_model_kicad_rotation_z_degrees": 90,
      "module_model_native_glb_transform_verified": "Source KiCad model rotation convention uses +90 degrees to obtain x=vendor_v+101 and y=vendor_u+26."
    },
    "connector_envelopes": {
      "DS50_mm": [
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      ],
      "DS24_mm": [
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      ],
      "DP50_mm": [
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      ],
      "DP24_mm": [
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      ],
      "meaning": "Supplier drawing outer envelopes only; no cavities, contacts, engagement, tolerances. Envelope overlap in assembled pose is not a physical collision check."
    },
    "qualification": [
      "Native PCB thickness/model datum discrepancy remains; do not infer exact 5mm seated BREP clearance.",
      "Original LDO generic header/regulator models reflect source CAD, installed population unverified.",
      "Source LDO J19 footprint has 24 signal-pad positions plus four source end pads; the end-pad function/numbering requires confirmation.",
      "No rail, interface, power-up, physical clearance or fabrication qualification."
    ],
    "models": [
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        "path": "models/DP24_Nominal_Envelope.step",
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        "path": "models/LDO_Native_Source.step",
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      {
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        "bytes": 15531
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      {
        "path": "models/DP50_Nominal_Envelope.step",
        "sha256": "008d378ceef665c33dd7729d44f01e881236d764925f104f63691cd8872f0394",
        "bytes": 15587
      },
      {
        "path": "models/XEM8305_Official.step",
        "sha256": "0da93f5624de23d671c20cbe4703904d300984273350cd30be9d544ab1248511",
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      {
        "path": "models/DS24_Nominal_Envelope.step",
        "sha256": "bdb39f8577d0293bf802b0e2849d501c5746b12d1d5cd8896cc4fc93073fed5f",
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    ],
    "connector_sources": {
      "DS50": "https://www.hirose.com/en/product/p/CL0684-4091-0-51",
      "DS24": "https://www.hirose.com/en/product/p/CL0684-4041-2-51",
      "DP50": "https://www.hirose.com/en/product/p/CL0684-4014-0-51",
      "DP24": "https://www.hirose.com/en/product/p/CL0684-4011-1-51",
      "download_status": "Exact vendor STEP ZIP links listed publicly; fresh direct retrieval returned HTTP 403; retained nominal drawing-derived envelope dimensions used."
    }
  },
  "composition": {
    "date_local": "2026-10-07",
    "output": "Assembly.glb",
    "output_sha256": "5d161e3b674dd9c28771b4c3911ea51b299e0984eee1ce477e2d88e240c76284",
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        "source_mesh_count": 17
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        "source_node_count": 235,
        "source_mesh_count": 103
      },
      {
        "group": "XEM8305",
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        "source_node_count": 439,
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    ],
    "limits": "Visual assembly only; inherited nominal 8.2 mm module top and 2 mm lower spacing. Amber J1/J19 connector bodies are supplier-drawing outer envelopes without contacts, cavities or seating detail. Exact seating and populated fit remain unverified.",
    "no_mesh_geometry_rewritten": true,
    "no_original_CAD_changes": true,
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        "material": "amber",
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        },
        "carrierworld_bounds_mm": {
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        "node_index": 703,
        "material": "amber",
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      {
        "key": "DP50",
        "step_source": "DP50_Nominal_Envelope.step",
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        "carrierworld_bounds_mm": {
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      "rotate": [
        290,
        0,
        0
      ],
      "zoom": 0.42,
      "requested_dimensions": [
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      ]
    },
    "render": "KiCad native basic quality, transparent background, no floor flag; camera/bottom1, top0.7, side0.8",
    "purpose": "Remove floor/shadow artifacts while preserving same35mm explodedstudy placement.",
    "output": "2026-10-07_FPGA_Work/01_Weekly_Meeting/revisions/R2_Assembly_First/visuals/Assembly_3D.png",
    "sha256": "46b781a24c1c677b1db84aa9d26a1c0686964a6de508addf15617a219f49e26c",
    "dimensions": [
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    ],
    "alpha_bounds": [
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    ],
    "opaque_bounds_alpha128": [
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    ],
    "frozen_native_study_sha256_after": "709b96f3eca8dde776fe58cc3427f70fa1b2d2b2dbd3f1d70cc1239666c385ba",
    "visual_qa": "PASS: all3boards visible and unclipped, no floor/shadow blocks, transparent background; native geometry unchanged."
  },
  "image_crop": {
    "box_pixels": [
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      448,
      1507,
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    ],
    "source_sha256": "46b781a24c1c677b1db84aa9d26a1c0686964a6de508addf15617a219f49e26c",
    "output_sha256": "d3627039fae432f5b815e3b123897f2a91c3d5de94b9a1a43fb1deb78d4d1263",
    "meaning": "Transparent margin crop only. Native geometry unchanged."
  }
}