5 October XEM8305 update: Direct LDO + XEM8305 connector review. The XEM8310/BRK8310 hardware below remains a separate dated project.
WEEKEND UPDATE · 3–4 OCTOBER 2026
I updated the XEM8305 carrier assembly view to include both mating connectors and checked the signal mapping through the flex cable. Separately, I traced the custom FPGA board’s power path: the XEM8310 carrier schematic already provides a protected path from the shared external supply to the custom micro-HDMI power contact. That carrier power routing and cable qualification are still unfinished. I have the assembly views and connection diagrams ready for review.
The XEM8305 backup carrier and XEM8310 receiver carrier are separate projects. The views below preserve the dated 29 September XEM8310/BRK8310 review.
EXISTING LAB HARDWARE
The purchased XEM8310 is an Artix UltraScale+ FPGA module used as the downstream receiver and controller; it is not a conventional MCU. BRK8310 is its separate breakout board. They currently mate directly through MC1, MC2 and MC3. In this dated 29 September study, a three-port interposer would be inserted at that joint so three remote XC7A25T boards can stream to XEM at the same time.
OFFICIAL BOARDS + PROPOSED INSERT
XEM and BRK mesh geometry is derived from Opal Kelly’s STEP files. Their direct-mate orientation is checked against the manufacturer’s mounting holes and connector locations. The displayed gap is deliberately exploded to reveal the proposed adapter. Its footprint, added stack height, fasteners, fansink and PCIe bracket have not passed a collision or assembly check.
CONNECTOR ROLES
Its underside MC3 is the high-speed vertical sandwich connector. It exposes twelve GTY channels, four in each of banks 226, 225 and 224. The proposed cables use three channels per bank for recording RX and the TX half of channel 0 for control.
Official contact list ↗Three Type-D receptacles would branch from XEM MC3 to three custom FPGA PCBs. Matching BRK high-speed contacts are left open to avoid Y stubs. The R7 logical schematic is checked; the R9 PCB routes six of twelve GTY pairs, but TX1 and control remain open on every cable.
Three-port MC3 pin table ↗J1 Bulls Eye exposes bank 226 in the direct stack. J6 is the computer PCIe card edge using banks 224/225. Those lanes are assigned to two custom cables in three-link mode, so J6 PCIe cannot run concurrently.
Official BRK guide ↗PC PATH AND POWER
The three remote FPGA boards use separate custom µHDMI cables and simultaneous XEM GTY links. XEM USB/FrontPanel is planned to deliver received samples to the PC. Link gateware, framing, buffering and sustained aggregate USB capture have not been measured.
See the three cable routes ↗The XEM does not generate a 12 V output for the remote boards. That earlier proposal called for a shared external 12 V input divided into three protected cable branches, while also supplying the XEM. The weekend update above records the protected schematic path in the separate current carrier review; its routing and cable qualification remain unfinished.
Manufacturer power guide ↗MANUFACTURER MECHANICAL FILES
The original STEP ZIPs remain at the manufacturer site. The browser uses derived lightweight meshes with conversion and orientation provenance. This visual study does not approve the new adapter outline or its physical mating.