WEEKEND UPDATE · 3–4 OCTOBER 2026
Over the weekend I worked on the FPGA board layout and design review, including the connector arrangement, power distribution, and routing approach. I completed the 3D component models and put together a review PDF with all 18 schematic sheets. I also contacted PCBWay to confirm the proposed eight-layer HDI stack-up and blind-via rules before committing to detailed routing. Routing is still unfinished, and I’m checking the timing constraints for the ASIC interface.
The weekend research revision is separate from the dated 29 September preview below. The existing preview geometry and counts describe that earlier project.
03 / CUSTOM RECORDING FPGA · 29 SEPTEMBER PREVIEW
The selected device in this dated review is XC7A25T-2CSG325I. Three separate custom FPGA PCBs were proposed, each with one custom 19-contact µHDMI cable to the XEM8310 interposer. This published native PCB retains the earlier 36 × 38 mm placement and two rigid DF40 connectors; its copper is unrouted and the DF40 interface was under redesign.
SELECTED 25T NATIVE SCHEMATIC · FOURTEEN SHEETS
These are native exports from the dated 29 September 25T review project. This dated preview is unrouted and retains the DF40 interface under review; it is separate from the weekend eighteen-sheet review. Open the complete FPGA schematic PDF ↗ · View the separate adapter schematic ↗
NATIVE PCB GEOMETRY
The board geometry comes from the dated 29 September XC7A25T KiCad project; the unavailable FPGA STEP body is represented by a simple 15 × 15 mm package shape. Component heights and the three-board spatial arrangement are illustrative. No cable fit, DF40 mating or full stack clearance is established. Read geometry provenance ↗
INTERFACE TO THE XEM8310
J4 contacts 3/5 and 6/8 send recording data on two active GTP transmitter pairs. 9/11 is a third transmitter pair physically wired but reserved in baseline firmware. 12/14 receives framed control from XEM. The custom FPGA generates ASIC CLK, DATA and LATCH locally.
J4.19 is a proposed 12 V input for the FPGA, routing and ASIC assembly. 1 is the target’s 1.8 V JTAG reference output; 2, 15, 17 and 18 are TMS, TDI, TCK and TDO. Source protection, current, return and a final programming method remain open.
The three cables enter separate XEM GTY banks: board A → 226, B → 225 and C → 224. Open the exact MC3 contact map ↗
BEFORE FABRICATION
The published 29 September 25T PCB has no tracks or vias. It needs controlled-impedance GTP routes, a reviewed stackup, power-entry protection, ASIC rail budget and layout/DRC review.
The existing two rigid DF40 sites are placement references. A floating-connector redesign, return contacts and power feed still need an approved carrier-to-FPGA map.
The 25T resource fit, GTY/GTP configuration, lane alignment and XEM receiver gateware require Vivado builds and hardware tests. The aggregate channel count across the three boards is still being confirmed.
The 28 September 50T board and purchasing review remains online as a historical placement checkpoint. Its BOM and selected device are not the current 25T choice.