{
  "date": "2026-09-29",
  "status": "Current R12 single-link layout study with preserved R8, R9 and R10 views. Exploded separation and cable paths are illustrative; fit and powered operation are unqualified.",
  "fpga25t": {
    "source": "2026-09-29_FPGA_Work/10_XC7A25T_Final_Device_Review/project/hardware/FPGA25T_8L_Unrouted.kicad_pcb",
    "source_sha256": "60244ee83bc00677245521e385cefbeb689a4519190349c38d34f51c7f970c82",
    "derived_asset": "fpga25t.glb",
    "derived_sha256": "76a179349775b31decf219f8d0d7acbfba5b5b5585fec8f8d9784adab921ba41",
    "export": "KiCad 10.0.6 pcb export glb; unavailable U1/U9 package bodies omitted from native export. Viewer adds an illustrative 15 x 15 mm U1 body. Board contains no routed tracks."
  },
  "xem8310": {
    "source": "https://www.opalkelly.com/products/models/",
    "step_download": "https://assets00.opalkelly.com/models/XEM8310-STEP.zip",
    "source_file": "XEM8310.STEP",
    "derived_asset": "xem8310-official.glb",
    "derived_sha256": "009e8f106c3f06d6efba4659bc271a322b4a95c47edba8832dd53f0e1c368ad4",
    "conversion": "OpenCascade STEP tessellation to glTF binary, official CAD geometry in mm and CAD Z-up; board and mating connectors kept at full tessellation, other components simplified for the browser; illustrative colors",
    "mating_transform_in_brk_cad_mm": "rotate 180 degrees around CAD Z, then translate (+167.65,+96.90,+6.395) for the nominal direct XEM-on-BRK stack",
    "viewer": "Both models are centered independently for an exploded architecture view. XEM is rotated 180 degrees in-plane and centered about (+34.825,-3.85) relative to BRK in viewer X/Z. Vertical gap is illustrative."
  },
  "brk8310": {
    "source": "https://www.opalkelly.com/products/models/",
    "step_download": "https://assets00.opalkelly.com/models/BRK8310-STEP.zip",
    "source_file": "BRK8310.STEP",
    "derived_asset": "brk8310-official.glb",
    "derived_sha256": "2db5cc50361182e78305aa4bca188c03fd5e32590e18c2453a34d690dd0080c3",
    "conversion": "OpenCascade STEP tessellation to glTF binary, official CAD geometry in mm and CAD Z-up; board and mating connectors kept at full tessellation, other components simplified for the browser; illustrative colors"
  },
  "interposer": {
    "source": "2026-09-29_FPGA_Work/16_BRK8310_Three_Port_Interposer_R9_GTY_Routing/project/BRK8310_Three_Port_Interposer_R9_GTY_Routing.kicad_pcb",
    "source_sha256": "28d8eee28226b8d2d575e136a41de9970fb336ba30b03f3bbaf79022fc3c5a60",
    "derived_asset": "r9-interposer-six-pair.glb",
    "derived_sha256": "560787b93a5bc7eef4bd8e8b50a52116f99485a928c5ebf92e3d10c58a581979",
    "export": "KiCad 10.0.6 PCB GLB export with native copper, pads and silkscreen. R9 is partial: 160 MC1/MC2 contacts and six GTY pairs routed (TX0 plus reserved TX2 per cable); TX1 and control remain open on every cable; 109 unconnected items. Physical DRC is clear only under provisional 0.15 mm study rules; 19 schematic-parity warnings remain. Power and JTAG circuits are not placed. Six custom stack connector 3D bodies are missing.",
    "frame": "KiCad export is in metres and Y-up. Viewer scales by 1000 and independently centers the geometry. In imported BRK KiCad XY, board outline x124.4..232.3261, y65.1536..135.1536 mm; subtract (64.676,38.254) mm to map to official BRK STEP XY. In viewer, its center sits x+29.86 mm, z-3.85 mm relative to BRK center; vertical exploded gap is illustrative.",
    "public_package": "hardware/xem8310-adapter/dated/2026-09-29/r9-six-pair/R9_Three_Port_Interposer_Public_Study.zip"
  },
  "interposer_r8": {
    "source": "2026-09-29_FPGA_Work/12_BRK8310_Three_Port_Interposer_R8_PCB_Study/project/BRK8310_Three_Port_Interposer_R8_PCB_Study.kicad_pcb",
    "source_sha256": "08dbc083b1a5abd51512d8d1b9d628381bc118a5c199b9bdcc2753c339353b7e",
    "derived_asset": "r8-interposer-partial.glb",
    "derived_sha256": "d874603b6ce04e715f94608c04994ab4102641cd8c6cc1cacfb938cd41d24322",
    "export": "KiCad 10.0.6 pcb export glb --include-tracks --include-pads --include-silkscreen; native project is partial: 160 MC1/MC2 contacts and one MC3-to-Type-D pair routed; 119 unconnected items; 61 conservative 0.20 mm physical DRC violations, zero geometry violations only under conditional 0.15 mm study rule. The 12 V protection/JTAG circuits are schematic placeholders, not placed. Six stack connector 3D bodies are missing from this export.",
    "frame": "KiCad export is in metres and Y-up. Viewer scales by 1000 and independently centers the geometry. In imported BRK KiCad XY, board outline x124.4..232.3261, y65.1536..135.1536 mm; subtract (64.676,38.254) mm to map to official BRK STEP XY. In viewer, its center sits x+29.86 mm, z-3.85 mm relative to BRK center; vertical exploded gap is illustrative.",
    "public_package": "hardware/xem8310-adapter/dated/2026-09-29/r8-partial-pcb/R8_Three_Port_Interposer_Public_Study.zip"
  },
  "interposer_r10": {
    "source": "2026-09-29_FPGA_Work/17_BRK8310_Three_Port_Interposer_R10_HDI_Feasibility/project/BRK8310_Three_Port_Interposer_R10_Full_Pair_Feasibility.kicad_pcb",
    "source_sha256": "6189239b3ee924bd9c2bc462f03491311253ff9f56e6a609af200e6002dca1cf",
    "derived_asset": "r10-interposer-hdi-feasibility.glb",
    "derived_sha256": "6a2a37485d4fa7b93b291b613ec28e8af2ed6972a700bac2d6d9ceca975b8d1e",
    "export": "KiCad 10.0.6 GLB with tracks, pads, inner copper and silkscreen. All 12 selected GTY pairs and 160 MC1/MC2 contact paths connected. Requires 12 proposed 0.25/0.10 mm F\u2192In1 microvias; provisional 0.15 mm clearance and 0.20 mm hole-copper. 0 physical DRC only under R10 study rules, 97 unconnected items, 19 parity issues. Pair coupling/impedance/length/skew and returnplanes unqualified. Power/JTAG incomplete. Six custom stack connector bodies missing. HDI process not selected. Optional feasibility view, not a selected fabrication process.",
    "frame": "KiCad export is in metres and Y-up. Viewer scales by 1000 and independently centers the geometry. In imported BRK KiCad XY, board outline x124.4..232.3261, y65.1536..135.1536 mm; subtract (64.676,38.254) mm to map to official BRK STEP XY. In viewer, its center sits x+29.86 mm, z-3.85 mm relative to BRK center; vertical exploded gap is illustrative.",
    "public_package": "hardware/xem8310-adapter/dated/2026-09-29/r10-hdi-feasibility/R10_Three_Port_Interposer_Public_Study.zip"
  },
  "interposer_r12": {
    "source": "2026-09-29_FPGA_Work/22_BRK8310_Single_Link_Interposer_R12/project/BRK8310_Single_Link_Interposer_R12.kicad_pcb",
    "source_sha256": "a1c2edf7554c58e6b5763d82b714bedd78e23a68d02884bb31c5cb4047131257",
    "derived_asset": "r12-interposer-single-link-study.glb",
    "derived_sha256": "e1f0f4affb1dae6b05fc4936f0bc045c83d0d6ef426aca75b80d72b4b54323a7",
    "export": "KiCad 10.0.6 native GLB export including tracks, pads, zones, inner copper and silkscreen. Single-link schematic maps all 19 numbered contacts with ERC 0; PCB retains 45 physical components. Independent copper audit: 10/19 contacts complete to all intended native endpoints, 8/8 serial conductors, 160 MC1/MC2 and 67 remaining MC3 pass-throughs, 13 isolated BRK contacts, no shorts. Current unsuppressed DRC: 0 physical errors, 11 dangling warnings, 9 opens, 0 parity issues. Four JTAG nets and ground branches remain open, including eFuse ground. Six custom stack connector 3D bodies are absent. Provisional HDI rules; no fabrication release.",
    "frame": "KiCad export in metres and Y-up; viewer scales by 1000. L-shaped outline extends x124.4..260 and y65.1536..135.1536 mm. The added right service wing shifts independently centered native geometry +13.837 mm in viewer X relative to historical outlines; existing stack connector centers are unchanged. Vertical separation and cable paths are illustrative, not mating/fit proof.",
    "public_package": "hardware/xem8310-adapter/dated/2026-09-29/r12-single-link/R12_Single_Link_Interposer_Public_Study.zip"
  }
}