Architecture & responsibility
Weekly review · 7 October: FPGA PCB and LDO presentation with major updates first, Zitong’s complete list, interactive native schematics and KiCad/3D views, and the next-week plan.
System overview
4K neural recording
Compact B · v1Assembly-first review
System architecture
Loading compact assembly…
ISOMETRICDrag to rotate · Scroll to zoom · Select a board
Compact STL · preserved geometryOverview stack · explanatory; open adapter page for official-model 3D
THREE-PORT RECEIVER PATH · 29 SEPTEMBER
Three FPGA boards → three cables → interposer → XEM8310
ASIC routing split TBD→3 × XC7A25T↔3 × µHDMI↔interposer routing study↔XEM8310 / BRK8310→USB / PC
Each FPGA has two active recording pairs, a wired but reserved third pair, and one reverse control pair. The proposed interposer assigns one XEM GTY bank to each cable. All three links are intended to run together over XEM USB. BRK J6 PCIe is a later alternate mode because its GTY lanes are used by two cables. The three protected 12 V cable branches, physical fit and link performance still need engineering proof.