Current connection direction · 5 October 2026
The original LDO board connects through a rigid routing board to XEM8305. This R2 native project includes MC1, MC2 and MC3, both LDO mating connectors, routed intended nets and filled ground copper.
KiCad exports from the frozen R2 native revision. Internal copper includes an In1.Cu DGND plane and mixed signal/DGND fill on In2.Cu. These outer-layer views do not qualify return paths, timing or manufacturability.
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Carrier only: native board, surface copper and pads, with five project-authored nominal socket boxes for MC1/MC2/MC3 and J1/J19. Manufacturer connector model bodies, other component bodies and the assembled XEM/LDO stack are omitted. Boxes illustrate position and side; they do not establish exact housing shape, height, seating or fit. Geometry receipt.
Connection scope
MC1 has 100 contacts; MC2 and MC3 each have 80. Every contact has an audited native pad and schematic disposition. MC3 connects its 28 DGND contacts; the other 52 contacts are explicitly reserved / no-connect. They do not implement a GTH link.
Both J1 and J19 are included for direct mating. J1 carries the mapped ASIC interface and named rails. J19 is preserved as a mechanical mating pair with explicit no-connect contacts. The candidate supplies the module bank rails and keeps the ADC ground reference separate; source, current, sequencing and load qualification remain open.
What still needs qualification
The returned clock is 68.476 mm and D_1–D_8 span 69.757–79.765 mm of native copper: an 11.29 mm group spread, with different via counts. These lengths do not establish propagation delay or the provisional ≤100 ps spread. Stack-up, local returns, ASIC setup/hold/data-valid limits and Vivado timing remain open.
J3 supplies XEM VDCIN; J4 supplies raw VIO 2.5 V ±2%; J5 supplies the original low-stage nominal 3.3 V feed. PG sequences the 1.5 V bank regulator and does not monitor ASIC rails. Actual load, limiting/startup, drop, plating and thermal behavior need qualification.
The carrier includes no automatic powered-off interface isolation, ASIC rail-ready monitor, ASIC hardware current limiter or accepted backfeed/stimulation cutoff. The original high-stage supplies and AGND return still need their accepted source/sequence contract. Firmware high-Z alone does not qualify the power sequence. Exact simultaneous seating, factory DFM and powered recording remain open.
Matching source files
Extract the whole ZIP and open hardware/LDO_to_XEM8305_Direct_R2.kicad_pro in KiCad 10.0.6. The project contains all four hierarchical sheets, project settings, symbol/footprint tables and local libraries. The two embedded Samtec model files are omitted from this public copy; their external references are documented. Electrical and board geometry semantics match the frozen source.
Fresh checks on the extracted public package report ERC 0, DRC 0, unconnected intended routes 0 and schematic/PCB parity 0. All error, warning and exclusion severities were checked; no checks are ignored or excluded. Full ERC receipt · Full DRC/parity receipt.
The independent assigned-net review passes 790 checks and the actual copper graph review passes 86 checks: all 23 J1→MC1 signals and all 32 multi-pad nets are connected in native copper. Their source bindings and limits are included in the public check summary.
Routed CAD candidate. Simultaneous seating, populated fit, ASIC electrical/timing limits, power/load/thermal behavior, FPGA firmware and factory DFM remain unqualified. These CAD checks do not establish powered recording or fabrication approval. The separate 35T R39 review retains its own status.
Preserved dated reviews
The A1R2 assembly and E5 adapter document the earlier cabled topology. Their saved mapping, copper and visualization checks apply to those revisions. The current direct arrangement requires its own native project and checks.