28 September 2026 · connector study

19 pins. One custom link.

Select a contact to see its proposed job on the XC7A50T board, beside Molex’s original Type-D drawing.

This is a custom electrical link, not an HDMI video port.

This historical page proposed a protected 5 V input on contact 19 while the native 50T schematic labeled its net LINK_12V. Howard later selected 12 V for the custom cable; the R7/R8 interposer study still lacks an implemented, protected source. Conventional Type-D HDMI assigns +5 V to contact 19, but an ordinary HDMI port is not a source for this custom map. Never connect ordinary HDMI equipment.

01 / PHYSICAL CONTACTS

The 19-contact plan

Look straight into the board receptacle’s mating opening. The numbered front view follows Molex sheet 2; this is a contact guide, not a fabrication footprint.

CUSTOM LINK · PROPOSAL

Our proposed use

XC7A50T · 2026-09-28

Front view looking into the board receptacle’s mating opening

board receptacle · mating face

Recording TXControl RXJTAGGround1.8 V reference5 V proposal

3 high-speed TX pairs → recording leaves the FPGA board ← 1 high-speed RX pair control enters the FPGA board

SELECTED CONTACT19 · Proposed protected 5 V input

One positive contact would receive power from a matching MCU-side board. The native 50T schematic still says LINK_12V; source current and cable limits remain unqualified.

Proposed 5 V · native LINK_12V mismatch

MANUFACTURER REFERENCE

Molex reference pinout

46765 series · sheets 2 and 4

Front view, looking into the board receptacle’s mating opening. This simplified redraw follows the contact numbering on Molex sheet 2; the manufacturer’s original is linked below.

TMDS pairsShields / groundControl+5 V

Data and clock: 3/5, 6/8, 9/11 and 12/14 form four TMDS pairs; 4, 7, 10 and 13 are their shields.

Other contacts: 1 is Hot Plug Detect; 2 Utility; 15 CEC; 16 DDC/CEC ground; 17 SCL; 18 SDA; 19 +5 V.

See Molex’s original sheets: sheet 2 front-view diagram ↗ · sheet 4 pin table / PCB layout ↗

Preview the original Molex PDF here

Some browsers block embedded PDFs. Use the direct sheet links above if this preview is blank.

Source and reading direction

Molex sales drawing SD-46765-001 for its Type-D receptacle family. The original PDF is linked from Molex’s website; this project does not host a copy. Check the exact J4 part and footprint against its approved drawing before layout release.

CLOCKING / PROPOSED SERIAL LINK

Where does the clock go?

Standard HDMI uses pins 12/14 as a TMDS clock pair. In this custom three-TX/one-RX proposal, those same contacts carry high-speed RX0 control data; there is no dedicated clock pair in the cable.

Across the cable

A GTP receiver recovers bit timing from each incoming high-speed data stream. That alone does not synchronize ASIC sampling; capture sync and timestamps remain open.

On the FPGA board

The GTP still needs a qualified differential reference clock at its MGTREFCLK inputs. Its frequency and jitter limits depend on the selected line rate. Those 50T connections are marked TBD; the legacy 32 MHz Y1 oscillator is disconnected and is not the GTP reference.

Other clocks

Pin 17 is JTAG TCK for programming only. Eight ASIC 32 MHz clocks return through J5 to the FPGA fabric. A shared ASIC clock and its distribution remain unresolved.

Clock choice changes the pin map: a forwarded-clock LVDS design would use one of these four cable pairs for clock, so its data-lane assignments must change. The proposed GTP link still needs a compatible serial receiver and protocol. AMD UG482 reference clocks ↗ · clock recovery ↗ · meeting clock action ↗

02 / CONTACT-BY-CONTACT

What changes on every pin

Directions are relative to the FPGA board. “Existing” means a named connection in the latest 50T schematic, not verified operation.

Pin	Proposed use on FPGA board	Conventional Type-D HDMI	50T design status
01	ReferenceVTREF 1.8 VOutput reference for a matching JTAG probe; no load supply.	Hot Plug Detect	Existing · VCCAUX_1V8
02	JTAGTMSMode select into the FPGA.	Utility	Existing · JTAG_TMS
03	Recording TXTX0+Positive half of high-speed recording lane 0, out.	TMDS Data2+	Proposed · unconnected
04	GroundGNDReturn and nearby pair reference.	TMDS Data2 shield	Existing · GND
05	Recording TXTX0−Negative half of high-speed recording lane 0, out.	TMDS Data2−	Proposed · unconnected
06	Recording TXTX1+Positive half of high-speed recording lane 1, out.	TMDS Data1+	Proposed · unconnected
07	GroundGNDReturn and nearby pair reference.	TMDS Data1 shield	Existing · GND
08	Recording TXTX1−Negative half of high-speed recording lane 1, out.	TMDS Data1−	Proposed · unconnected
09	Recording TXTX2+Positive half of high-speed recording lane 2, out.	TMDS Data0+	Proposed · unconnected
10	GroundGNDReturn and nearby pair reference.	TMDS Data0 shield	Existing · GND
11	Recording TXTX2−Negative half of high-speed recording lane 2, out.	TMDS Data0−	Proposed · unconnected
12	Control RXRX0+Positive half of high-speed control lane 0, in.	TMDS Clock+	Proposed · unconnected
13	GroundGNDReturn and nearby pair reference.	TMDS Clock shield	Existing · GND
14	Control RXRX0−Negative half of high-speed control lane 0, in.	TMDS Clock−	Proposed · unconnected
15	JTAGTDIProgramming data into the FPGA.	CEC	Existing · JTAG_TDI
16	GroundGNDCommon return for JTAG and power.	DDC/CEC ground	Existing · GND
17	JTAGTCKProgramming clock into the FPGA.	SCL	Existing · JTAG_TCK
18	JTAGTDOProgramming data out of the FPGA.	SDA	Existing · JTAG_TDO
19	Power proposalProtected 5 V inputOne positive contact from a matching MCU-side board; source current, load and cable are unqualified.	+5 V power	Proposed 5 V · native LINK_12V mismatch

Connector shell: separate from the 19 numbered contacts; proposed SHELL_GND, currently tied to GND. Its cable and chassis grounding still need review.

03 / BEFORE THIS IS A CABLE CONTRACT

What still needs to be checked

Electrical link

Assign the eight data contacts in the schematic, define the transmitter/receiver endpoints, coupling, protection, timing and receiver firmware.

Power path

Revise the native LINK_12V assignment before adopting 5 V. Measure the board-plus-ASIC load and qualify the source, cable, return path, voltage drop, faults and startup. Molex rates this receptacle at 0.8 A maximum per contact: one 5 V positive contact allows at most 4 W ideal connector-only, before cable or conversion losses. System current is unknown.

Physical continuity

Confirm the exact receptacle and cable part numbers, mating orientation, every contact, shell and PCB footprint against manufacturer drawings.