Recorded review · 28 September 2026
Make the FPGA board explainable before release.
The group reviewed FPGA supply, power and clocks, the mezzanine connection and the proposed micro-HDMI link to the MCU. The immediate work is a checked, block-by-block design and a concrete interface plan for the next review.
01 / Overview
What the meeting changed
- Design review comes before submission. Participants could not yet trace and explain every connection in the current multipage schematic. They agreed to rebuild or recheck the FPGA design in documented blocks against datasheets, starting with the device, power, clocks, configuration and connectors.
- FPGA ordering is on hold. The suggestion to order the 50T immediately was withdrawn. The next step is to ask an authorized distributor about exact-part availability and lead time for a few prototypes and a later larger quantity.
- The MCU interface needs a pin-level plan. The micro-HDMI pair allocation, return commands and JTAG access were discussed but not settled. The plan should be reviewed with Jiaao for firmware needs before the next Wednesday morning meeting.
Release status: this discussion did not approve a purchase, manufacturing submission, final pinout or replacement of the separately documented active CAD revision.
02 / PCB status
Board work by subsystem
| Workstream | Discussion and next check |
|---|---|
| ASIC / carriers | Confirm the clean input supply required by the ASIC-side LDOs. No new ASIC electrical requirement was established in this recording. |
| Routing / LDO | Check how the routing board receives power from the FPGA board, and whether the one-cable source can meet the load and noise requirements. A separate future power feed was raised as a possibility, not chosen. |
| FPGA | Build the schematic in explainable blocks; verify each component and rail, the GTP supplies and reference clock, flash capacity and useful test points. Keep two status LEDs: power and FPGA configuration. Two board-to-board connectors were favored for support; contact count and mounting details remain open. |
| Downstream / PC | Define the micro-HDMI-to-MCU signal map and command path. The receiving interface and firmware pin needs must be checked together. |
A small PCB prototype batch was discussed instead of a breadboard. The recording does not identify a new CAD commit, completed test or fabrication-ready revision.
03 / Interfaces
Checks needed before assigning pins
- Power: verify the actual cable input voltage and source, all FPGA and GTP rails, and the clean feed to ASIC LDOs. The inherited 12 V label was questioned during the meeting.
- Clock and boot: confirm the GTP differential reference clock, frequency, jitter and link-rate relationship from device documentation; choose flash capacity from the maximum configuration image size.
- MCU link: count micro-HDMI contacts, grounds, power, high-speed pairs and low-speed lines from the actual connector. Allocate FPGA-to-MCU data and MCU-to-FPGA control, then decide whether JTAG uses cable contacts or separate pads.
- Mechanical and test access: review two-connector placement, 60 versus 120 contacts, board orientation, mounting support and accessible FPGA I/O test points.
A three-transmit/one-receive high-speed split and use of low-speed lines for control were discussion options. They are not an approved micro-HDMI pin map.
04 / Decisions
Agreed direction and open choices
| Item | Meeting outcome | Still required |
|---|---|---|
| Review method | Use documented, datasheet-checked blocks that the team can explain before submission. | Complete the electrical review and identify the exact CAD revision. |
| Status indicators | Keep the power and FPGA-configuration LEDs; a third LED was not requested. | Confirm implementation in the revised schematic. |
| FPGA procurement | No part or quantity was approved for purchase. | Compare both candidate parts with an authorized distributor; confirm timing and stock. |
| Board connectors | Two connectors were favored for mechanical rigidity. | Select contact count, mating geometry, routing orientation and mounting approach. |
| MCU communication | No final cable pinout or protocol was agreed. | Verify the connector and review the plan with firmware. |
05 / Actions
Follow-ups from the recording
| Action | Owner / reviewer | Timing and evidence |
|---|---|---|
| Ask an authorized distributor when the candidate FPGAs can ship in prototype and roughly 100-unit quantities; ask Chong when the larger quantity is needed. | Owner TBD; Chong for schedule input | Contact was urged on 28 September. Completion or quote: not supplied. |
| Make a checked micro-HDMI pin map and FPGA↔MCU communication plan, including return commands and programming access. | Owner TBD; Jiaao to review firmware pin needs | Before the next Wednesday morning review. Calendar date 30 September is inferred from the recording date. |
| Build and document FPGA, power, clock, flash and connector blocks; independently compare power mapping where useful. | Owner TBD | Begin before Wednesday; no completed revised schematic supplied by this recording. |
| Check every component against its purpose and datasheet; compare with the SpikeGadgets board and plan useful test points. | Owner TBD | Before design release; no specific component removal approved. |
06 / Sources
Recording and dated context
The source is a 1:03:47 Voice Memo titled “Rice University,” recorded on 28 September 2026. This page summarizes its automatic transcript. The audio and transcript are retained privately with the local dated meeting handoff and are not published on this site. Automatic recognition may mishear technical terms, units and names; the recording and datasheets should be checked for precise engineering claims.
September 24 preparation remains a historical proposal with no outcomes recorded there. The current FPGA design pages document their own CAD and test status; this meeting summary does not change it.