The single-link schematic is implemented. The current native layout is in progress; ground and JTAG routes remain open.

Choose a sheet, zoom, then drag to inspect the pin labels. This is the preserved logical schematic carried from R8 into the routing studies; protected 12 V branches and JTAG headers remain circuit placeholders. Open the complete schematic PDF ↗ · View the separate custom FPGA schematic ↗

MANUFACTURING STUDY · PROCESS NOT SELECTED

Small blind vias solve the inner-contact escape.

R10 connects TX0, TX1, reserved TX2 and control for all three cables using twelve proposed 0.25/0.10 mm laser microvias. The independent audit confirms all 24 signal contacts and 160 MC1/MC2 paths. Physical DRC is clear under the documented HDI trial rules, but 97 items remain open. Power, JTAG, returns, impedance and pair matching are unfinished. A fabricator must qualify the via process and stackup before this route can be selected.

Inspect R10 in 3D ↗Download R10 KiCad project ↓Read exact rules and remaining work ↗

This is a connected-endpoint geometry study. Individually routed tracks are not yet a controlled-impedance, coupled differential channel. R9 remains the default 3D baseline; select “R10 · 12 pairs · HDI study” to see this optional native revision. Both earlier studies remain preserved.

PARTIAL BOARD FILE · OPEN IN KICAD

Six routed pairs, no complete cable link yet.

R9 traces TX0 and reserved TX2 on each of three cables and preserves all 160 MC1/MC2 pass-throughs. TX1 and the reverse control pair are open on every cable. KiCad reports zero physical violations at the provisional 0.15 mm study rule, 109 unconnected items, and 19 schematic-parity warnings. Power and JTAG hardware are still schematic placeholders. The first full-route attempt failed because ordinary through-vias collided with the Type-D connector keepout and other copper; its DRC record is preserved in the local R9 study.

Download R9 KiCad project ↓Read route limits and validation ↗

The six-pair route is a geometric study only. Its copper has no verified impedance, length matching, reference planes, cable loss, or complete data/control path. The 3D view uses the native R9 PCB export by default and offers the earlier R8 board as a separate selection; board fit and cable approach remain unverified.

BOARD FILE · OPEN IN KICAD

Three receptacles, one routed data pair.

R8 has 160 MC1/MC2 pass-through contacts routed and one MC3-to-Type-D pair as a routing sample. Another 119 items remain unconnected. The conservative 0.20 mm DRC reports 61 physical findings, and JTAG/power circuits are still schematic placeholders.

Download editable KiCad project ↓Read board status and source notes ↗

Select R8 in the 3D receiver view to load this earlier native PCB shape. Its stack connector bodies are absent from the KiCad export; the manufacturer's XEM/BRK models show their own connector geometry. Board placement, cable approach and vertical separation remain unverified.

Directions are relative to each custom FPGA: its recording TX pairs enter XEM RX pairs; XEM TX0 sends framed control back. The third recording pair is physically assigned but reserved in the current two-lane 25T plan. The three links are intended to operate together. In that mode BRK J6 cannot also use its x8 GTY paths.

This table follows the Opal Kelly XEM8310 pin list and the R7 five-page KiCad schematic. A GTY channel includes independent receive and transmit halves, so the candidate uses channel 0 RX for recording and channel 0 TX for control. GTY clocking, lane alignment and simultaneous transfer are not yet demonstrated.

The custom µHDMI cable assigns 12 V to contact 19, which is a nonstandard use of an HDMI connector. Do not mate it with ordinary HDMI equipment. Each of the three branches needs an explicit protected source, cable/contact current qualification and a power budget for its entire FPGA, routing and ASIC assembly.