4K / Meetings

01 / ASIC → FPGA

117 interface pins.

  1. 64
    Recording dataASIC 1–8 · DATA1–8
  2. 24
    Recording timingASIC 1–8 · CLK32MHz_Out, READ, SYNC
  3. 09
    Shared signalsCHIP_RESET · AC_IN · IMP_TST · FE_RESET
    SPI_LATCH · STIM_CLK · STIM_START · STIM_EN · STIM_CHB
  4. 04
    Recording clocksBOARD1–4_CLK
  5. 08
    Stim-chip programmingSTIM_CHIP1–4_SPI_DL / DR
  6. 04
    Nonstim programmingNONSTIM_BOARD1–2_SPI_DL / DR
  7. 04
    SPI clocksBOARD1–4_SPI_CLK

116 FPGA assignments + 1 external analog reservation: AC_IN.

Full 117-signal list ↗FPGA pin sheet ↗

02 / Custom micro-HDMI link

The 19-contact arrangement.

  1. 1
    VTREFTarget 1.8 V reference
  2. 2
    TMSProgramming state
  3. 3 / 5
    TX0 + / −Recording → XEM
  4. 6 / 8
    TX1 + / −Recording → XEM
  5. 9 / 11
    Reserved
  6. 12 / 14
    RX1 + / −Commands ← XEM
  7. 15
    TDIProgramming data
  8. 17
    TCKProgramming clock
  9. 18
    TDOProgramming readback
  10. 4 / 7 / 10 / 13 / 16
    GNDReference + return
  11. 19
    12 VProtected power input
Micro-HDMI · 19 contactsNumbering source ↗
Front of the board micro-HDMI socket. Upper row left to right: 19, 17, 15, 13, 11, 9, 7, 5, 3, 1. Lower row: 18, 16, 14, 12, 10, 8, 6, 4, 2. Contact colours match the signal list.
Front view · looking into the board socketCustom wiring
I have the schematic. All 19 contacts mapped ↗JTAG ↗12 V ↗

VTREF supplies translator bias. 12 V protection is drawn in the schematic; JTAG and ground routing remain open.

03 / Proposed components

FPGA board components

Zitong’s proposal · review pending

RoleProposed partKey specification
FPGAXC7A25T-2CSG325I ↗CSG325 · 15 × 15 mm
Status LEDs2 LEDsPower · configuration
Fabric clockAbracon AX3-0006-T ↗100 MHz · 1.8 V HCSL
Boot flashMacronix MX25U1632FZUI02 ↗16 Mbit · 1.8 V · USON-8
GTP reference clockSiTime SiT9507AI-02P1-1800-125.000000 ↗125 MHz · 1.8 V LVDS
Other partsMicro-HDMI · connectors · test pointsLDOs · regulators · inductors

Review: clock input / termination and flash bank voltages.

Part review ↗Current FPGA board ↗

04 / Full system plan

3 FPGA boards + XEM + BRK.

R10 architecture study · three separate FPGA boardsLayout in progressOpen system 3D ↗

System plan · finishing one 19-pin link first.

Current R12 layout ↗Interposer schematic ↗XEM + BRK ↗