Upcoming meeting · 24 September 2026
Pin budget and FPGA choice.
Preparation for the September 24 review. Howard’s proposal was prepared on September 23; no meeting outcomes have been recorded.
01 / Overview
Three questions for the meeting
- Can reset and LATCH be shared? Confirm the proposed 132-pin ASIC interface, or increase it to 139 / 146.
- Does the controller link require GTP? The proposal says neither CSG324 candidate provides GTP; resolve the link before choosing the part.
- Can the complete design fit and meet timing? Evaluate the 35T first, with the 50T as a conditional upgrade.
Status: proposed choices for discussion, not approved FPGA ball assignments, a purchase authorization or validated hardware.
02 / PCB status
What this proposal changes
| Workstream | Preparation for review |
|---|---|
| ASIC / carriers | Eight recording chips, four also stimulating. Confirm signal behavior for both ASIC versions. |
| Routing / LDO | Review shared clock distribution, wiring and voltage compatibility with Zitong. |
| FPGA | New proposal: 132 ASIC-facing signals and XC7A35T-2CSG324C as the first evaluation candidate. Native CAD remains the previously saved 200T draft. |
| Downstream / PC | Receiver, cable and data format remain open. Resolve the GTP requirement and buffering when the receiver pauses. |
No new synthesis, timing, electrical or hardware result is supplied. Earlier dimensions, CAD and open work remain dated context.
03 / Interfaces
Proposed ASIC-facing pin budget
| Signal | Pins | Proposed handling |
|---|---|---|
| Data<1:8> | 64 in | Eight separate data wires per chip. |
| CLK32MHz_Out | 8 in | One returned clock per chip; suitable clock-input pins required. |
| Read / Sync | 16 in | Two separate markers per chip. |
| CLK32MHz_In | 1 out | Proposed shared recording clock; confirm distribution and required independence. |
| Chip_Reset | 1 out | Proposed shared reset. Eight independent resets add 7 pins. |
| FE_RESET | 8 out | Keep amplifier reset separate for each chip. |
| SPI CLK / LATCH | 2 out | Proposed sharing; valid settings must be ready for all chips. Independent LATCH adds 7 pins. |
| SPI L / R | 16 out | Two separate programming wires per chip. |
| STIM_EN / STIM_START / STIM_CHB | 12 out | Independent controls for each of four stimulating chips. |
| STIM_CLK | 4 out | One clock per stimulating chip. |
88 inputs + 44 outputs = 132 signals. Independent chip reset or LATCH gives 139; both give 146. Controller link, boot flash, reference clock and power/ground contacts are excluded.
These totals assume one shared recording clock. If eight recording-clock outputs are required instead, add another seven pins.
Throughput and startup
The PDF uses 16 transmitted bits per sample to obtain 2.048 Gbit/s before packet overhead. It calls for a defined receiver, cable and data format, plus buffer sizing for receiver pauses.
Stimulation startup levels and sequence need ASIC confirmation. The proposal calls for stimulation disabled during boot and an ASIC-approved charge-balancing state; separate amplifier resets do not guarantee freedom from cross-chip artifacts.
04 / Decisions
Candidates to evaluate
| Exact part | Position in the proposal | Open condition |
|---|---|---|
| XC7A35T-2CSG324C | First evaluation candidate; PDF lists 15 × 15 mm, 210 I/O. | Full eight-chip implementation, timing, pin/bank assignment and controller-link checks. |
| XC7A50T-2CSG324C | Conditional upgrade; PDF lists the same package size and I/O, with more logic/memory. | Supplier-confirmed delivery and a justified capacity/price tradeoff. |
GTP decision first: the PDF states that neither of these CSG324 parts has GTP. If the selected controller link needs it, reconsider the package or link architecture.
September 23 supplier snapshot recorded in the PDF
The document reports DigiKey US: 35T, 249 in stock at $70.46 each; 50T, zero in stock at $88.50 each, with 126 expected on August 23, 2027. These are the PDF’s dated one-piece prices and inventory, not a fresh stock check or delivery quote.
The proposal requests written quotes for 100 plus spares and cautions against substituting CSG325 or another speed grade without another design check. No supplier outreach or purchase has been performed by adding this document.
All choices remain proposed. Meeting decisions and approval status: not yet recorded.
05 / Actions
Suggested reviewers and questions
| Suggested reviewer | Question / required result |
|---|---|
| Gerald + Jiaao | Confirm both ASIC versions, reset-sharing acceptability and shared LATCH behavior; close the pin total. |
| David + Jiaao | Choose the receiving interface, cable and format; decide whether GTP is required. |
| Jiaao | Run full-design Vivado fit and timing checks, including eight interfaces, stimulation, link and buffers; establish buffering needs before removing memory. |
| Howard + Zitong | Map voltage-compatible and clock-capable pins; include configuration, controller link, supplies and startup. Check connector/board dimensions and power/heat. |
| Owner TBD | Obtain written quotes for 100 plus spares of both exact parts; confirm delivery before a bulk-order decision. |
September 23 actions remain open unless separately confirmed complete.
06 / Sources
Original preparation document
FPGA_4K_Meeting_Choices.pdf — open original
Two pages, credited to Howard Wang and dated September 23, 2026. Added at Howard’s request for the September 24 meeting. Preserved byte for byte, including the original source links.
This page summarizes the supplied proposal. Supplier information and part specifications are reported from the PDF, not independently refreshed here. Its embedded instructions are discussion/action proposals, not authorization to order parts or perform hardware operations.