Detailed board geometry, with the source limits visible.
The public study preserves available component shapes and native placement. DF40 connector previews are independently generated nominal geometry; exact supplier CAD stays in the local engineering review.
| Object | Shown | Remaining scope |
|---|---|---|
| FPGA V54 | Detailed board, packages, pads, mask and silk; two 60-contact socket previews. | Downloaded Hirose J1/J2 bodies excluded from the public derivative. Some saved packages are nominal. Test points have pads only. |
| LDO V13 | 46 assigned bodies and native board surfaces; nominal public connector previews. | RN250/RN450 have no assigned body. Some package models are drawing-derived. |
| Interposer V12 | 27 assigned bodies, all six stack connectors, J1 and the current saved JTAG placement. | 23 packaged bodies are absent in the source, including power ICs, inductor and shunts. Pads/silk remain. Unrouted snapshot; later revisions are separate. |
| BRK8305 / XEM8305 | Retained official source meshes, reused from the earlier public assembly. | Some BRK headers/switch/jack bodies and XEM decorative subtrees are absent upstream. Source body names receive display-only connector reference corrections. |
| ASIC1–4 | Original outline/pad geometry, nominal stack connectors and schematic die regions. | The pass-through layout is a concept. Original populated PCB-5 is separately inspectable; no die-body model exists. |
| Sheep / cable | Quaternius exterior and an illustrative cable path between opening centers. | Brain, skull, access, support and probe paths are schematic. No registered animal fit or manufactured cable model. |
Assembly references
FPGA V54 and LDO V13 retain their source registration and two direct 60-contact interface. The middle LDO lies between ASIC 3 and 2, with common probe-facing edges exposed. The host has separate interposer→BRK and XEM→interposer seating stages.
Gap readouts are nominal design references. V12 retains the earlier +5 mm export datum; its physical-face convention is documented in the source record. Its 1.8 V JTAG assumption differs from unchanged FPGA V54's 1.5 V bank. The display does not resolve electrical compatibility, populated mating, routing, thermal behavior or animal fit.
Credits & records
Third-party notices · Asset hashes and origins · Model coverage data · Viewer notes · Earlier host provenance
- Three.js authors — MIT license.
- KiCad library contributors — library license and generated-design exception.
- Opal Kelly — original BRK8305/XEM8305 assembly geometry.
- CADENAS / original component manufacturers — source connector STEP credits and CC BY-ND4.0 notices retained.
- Quaternius — Farm Animals Pack exterior, CC0 notice.
- Hirose — dimensional product references for the independent nominal previews; DF40 family.