Wednesday 21 October · FPGA hardware · V2

Weekly update

  • LDO carrier board

    Ready for manufacturing. JLCPCB global sourcing comes first.

  • XEM to FPGA interposer

    Schematic and routing complete. Component sourcing started.

  • Separate FPGA and LDO boards

    Full assembly overview and a closer look at the FPGA board.

  • FPGA board

    Updated oscillators, configuration and schematic drawing.

LDO carrier board progress

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JLCPCB global sourcing · 20 October 2026 · prices and Purchasing status from the saved screenshot.

Ready for manufacturing. We are globally sourcing the components through JLCPCB first.

System assembly overview

Assembly animation: ASIC boards, LDO, FPGA and the XEM host.

XEM to FPGA interposer schematic

  • Power12 V to XEM. Protected 3.3 V to the remote FPGA.
  • Serial linkThree data pairs to XEM and one command pair back.
  • ProgrammingBRK USB JTAG. Edge switch selects XEM or remote FPGA.
  • SourcingStarted component sourcing ahead of manufacturing this week.
100%Open drawing
V23 one-page schematic with the updated PCM12 selector switch.

V23 one-page schematic with the updated PCM12 selector switch.

Review with Gerald and Zitong. Manufacturing target: this week.

Separate FPGA and LDO boards

All boards in the overview. Use FPGA close-up or select a component to zoom in.

Interposer schematic, layout and 3D

V23: updated PCM12 selector switch, schematic and routing. Review with Gerald and Zitong.

FPGA schematic updates

  • PowerBank 0, JTAG and flash share 1.8 V. ASIC I/O banks stay at 1.5 V.
  • ConfigurationSPIx1 boot path with separate PROGRAM_B and INIT_B holds.
  • Clock125 MHz GTP reference plus a separate 25 MHz fabric clock.
  • DrawingSupport parts connect directly to their local circuits on one page.
100%Open drawing
V60 one-page schematic, retaining the oscillator, configuration and directly wired support circuits.

V60 one-page schematic, retaining the oscillator, configuration and directly wired support circuits.

FPGA oscillators and layout

125 MHz GTP reference and separate 25 MHz fabric clock. V60 adds local regulator routing. Full board routing continues.

Next steps

  1. Finish carrier component sourcing and move into manufacturing
  2. Review the interposer with Gerald and Zitong
  3. Continue interposer component sourcing for manufacturing this week
  4. Confirm the separate FPGA/LDO arrangement and ASIC connections
  5. Continue FPGA layout and routing after the schematic updates

Presentation notes

Prepared 20 October for the 21 October meeting. Presenter notes and source references.

Use the arrow buttons or Page Up / Page Down. Expand view enlarges the active drawing or CAD model. Notes are hidden until selected.

Previous meeting, 14 October V17