Wednesday 14 October · Carrier / FPGA

Weekly update

  • Carrier

    Quick email review with Gerald, Zitong and JLCPCB; revised a few issues.

  • FPGA schematic

    Power, pinout, clock and configuration on one page.

  • FPGA routing

    116/116 digital mezzanine paths connected.

XEM8305 / LDO carrier

V16 carrier. Nominal CAD assembly; populated fit remains to verify.

Carrier board schematic

  • Power12 V powers XEM8305; an onboard buck provides 3.3 V to the LDO board.
  • PinoutEight data lines plus clocks, SPI, reset and stimulation control at 1.8 V.
  • ProgrammingUSB-C JTAG bridge with 1.8 V level translation. USB powers the bridge only.
  • ConnectorsMC1/MC2 connect XEM8305; the 50-pin J1 links the LDO board.
100%Open drawing
V16 one-page carrier schematic

Carrier layout and routing

Completed one email review round with Gerald, Zitong and JLCPCB, then revised several issues.

FPGA PCB schematic

  • Power3.3 V input; onboard 1.0 V core, 1.8 V auxiliary and 1.5 V I/O rails.
  • PinoutJ1/J2: two 60-pin connectors for eight ASICs’ data, clocks, SPI and control.
  • Clock125 MHz differential reference to GTP REFCLK0; also used by FPGA logic.
  • ConfigurationFlash stores the FPGA image; direct JTAG supports programming and debug.
100%Open drawing
Current one-page FPGA schematic

FPGA layout and 3D

25 × 23 mm. Mezzanine routing complete; timing and remaining board routing continue.

FPGA and LDO boards

Next steps

  1. Order the carrier board
  2. Work out how to connect the ASIC boards together and to the LDO board
  3. Decide whether to use a combined FPGA + LDO PCB
  4. Complete the LDO board schematic
  5. Complete FPGA PCB routing

Presentation notes

Updated 14 October; source versions identified in the views. Open the short presenter notes.

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