{
  "revision": "R12",
  "date": "2026-10-09",
  "source_pcb_sha256": "7080ee9740a6ef007f2263a29c9db14506117d780382839fcd4e2ccd93943d2f",
  "public_render_pcb_sha256": "c15821caf7019d6459111c79fa384b5c869bbc5ce768a259a357839fe641c5ee",
  "public_scope": "Four native CAD-rendered PNG review views, interactive GLB, schematic PDF and provenance; no native supplier model collection published.",
  "component_bodies": 75,
  "intentionally_bare": [
    "MH1",
    "MH3",
    "MH4",
    "MH2",
    "TP20",
    "TP19"
  ],
  "public_geometry_substitutions": [
    "J1",
    "J19",
    "MC1",
    "MC2",
    "MC3",
    "J4"
  ],
  "substitution_method": "Independently authored primitives using native pad positions and nominal mechanical facts. No restricted supplier STEP, embedded geometry or derivative mesh imported into these six representations.",
  "other_bodies": "69 KiCad stock package or original dimension-derived assignments.",
  "attribution": {
    "KiCad": "https://www.kicad.org/libraries/license/",
    "license": "CC BY-SA 4.0 with electronic-design/generated-file exception",
    "details": "Visual_Sources.md"
  },
  "source_native_unchanged": true,
  "R11_source_unchanged": true,
  "electrical_layout_and_rules_unchanged_in_render_copy": true,
  "recursive_embedded_node_count": 0,
  "supplier_permission_claimed": false,
  "image_metadata": [
    {
      "file": "Carrier_R12_Bottom.png",
      "sha256": "0ee9d2f3e8f0a0da449fcb480b7d0a22b9e3c840d7203297b42e984929e24447",
      "bytes": 520200,
      "dimensions": [
        1768,
        1488
      ],
      "mode": "RGBA",
      "alpha_extrema": [
        0,
        255
      ],
      "opaque_bbox": [
        454,
        71,
        1314,
        1428
      ],
      "opaque_margins": [
        454,
        71,
        454,
        60
      ],
      "CLI_success": true
    },
    {
      "file": "Carrier_R12_Bottom_3D.png",
      "sha256": "addc90f8f619a804e978c503254bda71c5c2b4aee8cad307e9f03ea2219acb54",
      "bytes": 434372,
      "dimensions": [
        1768,
        1488
      ],
      "mode": "RGBA",
      "alpha_extrema": [
        0,
        255
      ],
      "opaque_bbox": [
        427,
        244,
        1340,
        1233
      ],
      "opaque_margins": [
        427,
        244,
        428,
        255
      ],
      "CLI_success": true
    },
    {
      "file": "Carrier_R12_Top.png",
      "sha256": "9a94d704a1d5e5061436773db1ce02cb27e5bd4eca338fe9ba6ba11b599b6245",
      "bytes": 554480,
      "dimensions": [
        1768,
        1488
      ],
      "mode": "RGBA",
      "alpha_extrema": [
        0,
        255
      ],
      "opaque_bbox": [
        454,
        71,
        1314,
        1428
      ],
      "opaque_margins": [
        454,
        71,
        454,
        60
      ],
      "CLI_success": true
    },
    {
      "file": "Carrier_R12_Top_3D.png",
      "sha256": "c9648fff033ab2f3fb6b7b4e6a15b9bdf11b435ec9d4a7eded3f20a2d5206cc5",
      "bytes": 383955,
      "dimensions": [
        1768,
        1488
      ],
      "mode": "RGBA",
      "alpha_extrema": [
        0,
        255
      ],
      "opaque_bbox": [
        427,
        228,
        1340,
        1233
      ],
      "opaque_margins": [
        427,
        228,
        428,
        255
      ],
      "CLI_success": true
    }
  ],
  "export_warning": "Native KiCad GLB export reported wire self-interference near MC2 at z=1.5994 mm, x105.790898..107.008146/y86.001335..86.832516. A small local exported copper surface may be incomplete. Use native PCB routing SVGs for exact traces; this mesh is a visualization.",
  "limits": [
    "Generic package models are illustrative, not exact mating/tolerance geometry.",
    "Static checks do not establish powered operation or fabrication readiness."
  ],
  "files": [
    {
      "path": "Carrier_R12_Bottom.png",
      "bytes": 520200,
      "sha256": "0ee9d2f3e8f0a0da449fcb480b7d0a22b9e3c840d7203297b42e984929e24447"
    },
    {
      "path": "Carrier_R12_Bottom_3D.png",
      "bytes": 434372,
      "sha256": "addc90f8f619a804e978c503254bda71c5c2b4aee8cad307e9f03ea2219acb54"
    },
    {
      "path": "Carrier_R12_Check_Summary.json",
      "bytes": 2370,
      "sha256": "66713bf4b474175d133189a3f14d80fa28a61120fef880e9cab1f978a9e38d43"
    },
    {
      "path": "Carrier_R12_Interactive.glb",
      "bytes": 15868028,
      "sha256": "19a3d293e62c401b85d58ad5e696b5b5053795eda9382947f615470e151285e9"
    },
    {
      "path": "Carrier_R12_Routing.svg",
      "bytes": 1195118,
      "sha256": "6a06c8a09e294f40e707f3649175a3371c0f235382b8e260a78db3599d53af10"
    },
    {
      "path": "Carrier_R12_Schematic.pdf",
      "bytes": 522043,
      "sha256": "28ba8d64b1cf961768865cc63c7965bd9cd428f48a6e964aea3a08ed71c909d4"
    },
    {
      "path": "Carrier_R12_Top.png",
      "bytes": 554480,
      "sha256": "9a94d704a1d5e5061436773db1ce02cb27e5bd4eca338fe9ba6ba11b599b6245"
    },
    {
      "path": "Carrier_R12_Top_3D.png",
      "bytes": 383955,
      "sha256": "c9648fff033ab2f3fb6b7b4e6a15b9bdf11b435ec9d4a7eded3f20a2d5206cc5"
    },
    {
      "path": "Interactive_Model_Provenance.json",
      "bytes": 2774,
      "sha256": "ae28e790304ef50217bdbe932793d932ee42cefcda1ee2fcaefd5927c6b57d87"
    },
    {
      "path": "Mating_Clearance_R12.png",
      "bytes": 120036,
      "sha256": "eff6b2aaf61c13a1fe62bf7f044d2c528971b942139bdcb4df7e36efc2b1dfa2"
    },
    {
      "path": "Visual_Sources.md",
      "bytes": 3672,
      "sha256": "25ec45f7484401207ea15d2c459ca705b3a137502555c93c1b4a516d42f5844a"
    }
  ],
  "mating_diagram": {
    "file": "Mating_Clearance_R12.png",
    "sha256": "eff6b2aaf61c13a1fe62bf7f044d2c528971b942139bdcb4df7e36efc2b1dfa2",
    "source_LDO_PCB_sha256": "74ed99fa1a91cc73ad9b93946fd1b386a5a99355ad15efb51276b0db660e3425",
    "registration_mm": {
      "x": "x_ldo - 52.3",
      "y": "71.45 - y_ldo"
    },
    "description": "Native LDO outline registered by both mating connector centers; nominal body envelopes compare R11 D4 overlap and R12 clearance. Physical seating/orientation/tolerances remain unqualified."
  }
}