The ASIC boards now show the PCB-5 source outline and bondout-pad positions, with nominal 8.1 × 7 mm die bodies. See ASIC model details. The thinner profile uses 0.8 mm substrate and a 1.5 mm gap between ASIC boards as a visual proposal; the upper LDO/ASIC spacing is left larger while clearance is reviewed; the connectors shown are schematic placeholders. Earlier profile is 1.6 mm / 3.0 mm. No connector or PCB thickness has been selected. Eight copies represent the proposed architecture; cables and model registrations are illustrative. The Artix-7 FPGA uses the earlier V60 physical PCB model; its latest interface changes are schematic-only. The separate LDO is V13 and is not qualified. The breakout shown is the retained review snapshot. The PC tower and internal slot are schematic context; their scale and arrangement are illustrative. The teal path starts at J6’s actual card-edge center and shows the logical PCIe x4 host connection. The board has an x8-length physical edge, so the host needs an x8-or-larger compatible slot. No cable, riser or enclosure has been selected or mechanically validated. XEM-to-breakout mating and all stack fit remain unverified. SpikeGadgets MSH manual, p. 4 shows 70/80-pin stacking connectors, but does not establish thickness or gap.