CHAPTER 01 / POWER & GROUND
Follow the power.
Find its way back.
A guided look at the actual V32 layout. Start at the 12 V jack, then zoom into the regulator and its ground returns.
Review snapshot · fixes are still proposals
12 V input
FROM REVIEW TO A BETTER LAYOUT
The next routing pass, in order.
These are open actions. The V32 copper shown above has not been changed.
- Define the inputChoose the adapter, polarity, current limit and fault conditions; coordinate protection before laying it out.
- Plan quiet and power returns togetherGive R78/C55 a quiet SGND connection and one deliberate local PGND join. Remove unintended bypasses without splitting the board’s reference planes.
- Compare local capacitor placementOptimize the complete C47/C48 loop, preserve compact SW/C53, and place the C56 candidate with a short PGND return.
- Choose a deliberate sense pickupRoute the output sense from the output-capacitor region, away from SW and shared load-current drops.
- Check the exact revised boardRefill, run native connectivity / DRC / parity, inspect the returns, then measure startup, ripple, load response and temperature under defined conditions.
EVIDENCE & BOUNDARIES
What this view can tell us.
Native geometry establishes where copper connects. It does not establish how much current takes each path, whether the regulator is stable, or whether the board is ready to manufacture.
Exact board and display method
Source: CARRIER_XEM8305_V32_Clean_Bundle.kicad_pcb. Bottom copper is shown in an unmirrored top view. Component outlines are projected on inner layers; surface pads appear only on their actual layers. Display polygons are simplified by at most 0.008 mm, then rounded to 0.001 mm.
SHA-256:
Read-only review: 13 selected power/control net groups were connected, 88 displayed pad/net anchors matched native evidence, and 30 local DGND vias contacted both In1 and In4 ground fills. This website does not claim a new DRC run.
Derived geometry and measured bypass corridors · Provenance and review scope
Manufacturer guidance
TI TPS54429E, SLVSAS0, February 2011 — p.5 RSA pin mapping; p.15 capacitor guidance; p.16 layout items 1–14. The pictured PWP layout is not this board’s RSA footprint.
TI EVM, SLVU444A, revised August 2021 — §6.1 p.14 grounding; p.18 C6 example. The EVM is guidance, not a drop-in layout.
Diodes SMBJ family — p.3 SMBJ15CA ratings. A clamp rating applies at its stated test current.
What remains unknown
The exact adapter, polarity, load-current budget, fault energy and measured regulator performance remain open. C56’s V27 proposal is separate from V32. ASIC timing and USB-JTAG integration are separate reviews.