{
  "native_format": "KiCad 10",
  "audit": "../../../hardware/fpga-interface-study/dated/2026-09-27/usb-c-revision/reports/USB_C_Native_Audit.json",
  "boards": [
    {
      "id": "fpga50t",
      "title": "50T micro-HDMI \u00b7 36 \u00d7 38 mm \u00b7 unrouted review",
      "description": "Compact XC7A50T review with two 60-contact DF40T ASIC connectors, 174 footprints and 625 native ratsnest links. Eight copper layers, no tracks or vias; mechanical mating, power, link and manufacturing checks remain open.",
      "native": "../../../hardware/fpga-interface-study/dated/2026-09-28/50t-two-60-compact/project/hardware/FPGA50T_8L_Unrouted.kicad_pcb",
      "project": "../../../hardware/fpga-interface-study/dated/2026-09-28/50t-two-60-compact/project/hardware/FPGA50T_8L_Unrouted.kicad_pro",
      "zip": "../../../hardware/fpga-interface-study/dated/2026-09-28/50t-two-60-compact/FPGA50T_Two_60_Compact_Review_2026-09-28.zip",
      "svg": "fpga50t-front.svg",
      "sha256": "6bafa7f2b19bca1b78f083b53e7d6f9c46c5619e1202761e4f698e362bb01a54",
      "dimensions_mm": [
        36.0,
        38.0
      ],
      "expected": {
        "footprints": 174,
        "pads": 911,
        "segments": 0,
        "vias": 0,
        "zones": 0,
        "fpgaPads": 324,
        "copperLayers": 8,
        "nets": 236
      },
      "unconnected_items": 625,
      "manufacturing_ready": false,
      "drc_reported_unconnected_items": 499,
      "package_manifest": "hardware/fpga-interface-study/dated/2026-09-28/50t-two-60-compact/manifest.json",
      "publication_status": "Compact 50T unrouted engineering review; not for manufacture"
    },
    {
      "id": "compact-routed",
      "title": "Preserved micro-HDMI \u00b7 33 \u00d7 36 mm \u00b7 125 parts",
      "description": "Historical micro-HDMI checkpoint. 125 parts; 116 candidate FPGA nets plus one analog reservation; 116/116 candidate nets copper-connected. 0 total assigned-net gaps remain. Power integrity, ASIC electrical limits and timing remain unverified; receiver deferred.",
      "native": "../../../hardware/fpga-interface-study/dated/2026-09-27/completion-checkpoint/hardware/FPGA100T_33x36_Routing.kicad_pcb",
      "zip": "../../../hardware/fpga-interface-study/dated/2026-09-27/completion-checkpoint/FPGA100T_33x36_Routing.zip",
      "svg": "../../../hardware/fpga-interface-study/dated/2026-09-27/completion-checkpoint/output/FPGA100T_33x36_Routing.svg",
      "sha256": "2975050c28c89fc96bf781cf082bffffc84189e6720ce05c4200d8552ac298fc",
      "expected": {
        "footprints": 125,
        "pads": 801,
        "segments": 3123,
        "vias": 546,
        "zones": 13,
        "fpgaPads": 324,
        "copperLayers": 12,
        "nets": 263
      },
      "unconnected_items": 0,
      "manufacturing_ready": false,
      "dimensions_mm": [
        33.0,
        36.0
      ],
      "project": "../../../hardware/fpga-interface-study/dated/2026-09-27/completion-checkpoint/hardware/FPGA100T_33x36_Routing.kicad_pro"
    },
    {
      "id": "usb-c",
      "title": "USB-C revision \u00b7 33 \u00d7 36 mm \u00b7 development",
      "description": "178 fitted parts plus one copper-only recovery fixture. 91/116 ASIC FPGA-to-connector paths connected; 268 total assigned-net open items, 0 DRC errors and 394 warnings. USB-C power/control and custom four-pair data link require matching firmware and receiver. Not for manufacture.",
      "native": "../../../hardware/fpga-interface-study/dated/2026-09-27/usb-c-revision/hardware/FPGA100T_33x36_Routing.kicad_pcb",
      "project": "../../../hardware/fpga-interface-study/dated/2026-09-27/usb-c-revision/hardware/FPGA100T_33x36_Routing.kicad_pro",
      "zip": "../../../hardware/fpga-interface-study/dated/2026-09-27/usb-c-revision/FPGA100T_USB_C_Development.zip",
      "svg": "../../../hardware/fpga-interface-study/dated/2026-09-27/usb-c-revision/output/FPGA100T_33x36_Routing.svg",
      "audit": "../../../hardware/fpga-interface-study/dated/2026-09-27/usb-c-revision/reports/USB_C_Native_Audit.json",
      "sha256": "c2bb9d1de754b65ebb3076b0b2c97529bc77afb4e5efad52e5762c3a9af2ac76",
      "expected": {
        "footprints": 179,
        "pads": 1064,
        "segments": 3480,
        "vias": 549,
        "zones": 13,
        "fpgaPads": 324,
        "copperLayers": 12,
        "nets": 320
      },
      "unconnected_items": 268,
      "manufacturing_ready": false,
      "dimensions_mm": [
        33.0,
        36.0
      ]
    },
    {
      "id": "core",
      "title": "Earlier core \u00b7 40 \u00d7 36 mm",
      "description": "126 parts; partial core wiring. The 117 ASIC signals and data link are not assigned. 139 existing-net connections remain open.",
      "native": "../../../hardware/fpga-100t-review/hardware/FPGA100T_Minimal.kicad_pcb",
      "zip": "../../../hardware/fpga-100t-review/FPGA100T_Review_Project.zip",
      "svg": "../../../hardware/fpga-100t-review/output/FPGA100T_Minimal_PCB.svg",
      "sha256": "3844c24f88697bec091e872c117a7889586df9be4053b912ec79253738d337c0",
      "expected": {
        "footprints": 126,
        "pads": 675,
        "segments": 1010,
        "vias": 146,
        "zones": 4,
        "fpgaPads": 324,
        "copperLayers": 6,
        "nets": 265
      },
      "unconnected_items": 139,
      "manufacturing_ready": false,
      "dimensions_mm": [
        40,
        36
      ]
    },
    {
      "id": "rail",
      "title": "Rail revision \u00b7 separate proposal",
      "description": "128 parts; separate 1.8 V configuration / 2.5 V link-bank revision. 347 existing-net connections remain open. Mezzanines and complete ASIC wiring are absent.",
      "native": "../../../hardware/fpga-interface-study/native/FPGA100T_Full_System.kicad_pcb",
      "zip": "../../../hardware/fpga-interface-study/review_projects/FPGA100T_Rail_Revision.zip",
      "svg": null,
      "sha256": "c71578d3e72d22d84c3cf635c6935c736940c9ae5b3f8de2a5dd404a9f00a547",
      "expected": {
        "footprints": 128,
        "pads": 679,
        "segments": 360,
        "vias": 25,
        "zones": 0,
        "fpgaPads": 324,
        "copperLayers": 6,
        "nets": 266
      },
      "unconnected_items": 347,
      "manufacturing_ready": false,
      "dimensions_mm": [
        40,
        36
      ]
    },
    {
      "id": "mezzanine",
      "title": "Mezzanine fit \u00b7 placement only",
      "description": "128 parts; two 60-contact connectors as a placement study. No tracks, vias or filled zones; no integrated schematic. All 120 numbered connector contacts are unassigned.",
      "native": "../../../hardware/fpga-interface-study/native/FPGA100T_Mezzanine_Fit.kicad_pcb",
      "zip": "../../../hardware/fpga-interface-study/review_projects/FPGA100T_Mezzanine_Study.zip",
      "svg": "../../../hardware/fpga-interface-study/mezzanine/Mezzanine_Fit.svg",
      "sha256": "186018ad28d31eb3d8fee4193a32731632a9bf9cab2c4652414a9bad40169750",
      "expected": {
        "footprints": 128,
        "pads": 807,
        "segments": 0,
        "vias": 0,
        "zones": 0,
        "fpgaPads": 324,
        "copperLayers": 6,
        "nets": 265
      },
      "unconnected_items": 383,
      "manufacturing_ready": false,
      "dimensions_mm": [
        40,
        36
      ]
    },
    {
      "id": "compact",
      "title": "Smaller fit \u00b7 37.5 \u00d7 36 mm \u00b7 placement only",
      "description": "128 parts in a separate 37.5 \u00d7 36 mm placement study, including both 60-contact mezzanines. No tracks, vias, zones or integrated schematic; all 120 numbered connector contacts remain unassigned. C92/R122 rail additions and proposed input protection are absent. 383 existing-net connections remain open.",
      "native": "../../../hardware/fpga-interface-study/size_optimization/candidate/hardware/FPGA100T_37p5x36_Placement.kicad_pcb",
      "zip": "../../../hardware/fpga-interface-study/size_optimization/candidate/FPGA100T_Compact_Study.zip",
      "svg": "../../../hardware/fpga-interface-study/size_optimization/candidate/output/Compact_Front.svg",
      "sha256": "2487779b7b0b612c0452388cd41be21a51cf6b1594e8a389b0c38f23de733865",
      "dimensions_mm": [
        37.5,
        36
      ],
      "expected": {
        "footprints": 128,
        "pads": 807,
        "segments": 0,
        "vias": 0,
        "zones": 0,
        "fpgaPads": 324,
        "copperLayers": 6,
        "nets": 265
      },
      "unconnected_items": 383,
      "manufacturing_ready": false
    },
    {
      "id": "compact-v2",
      "title": "Earlier 33 \u00d7 36 mm placement \u00b7 128 parts",
      "description": "128 parts in the 26 September 33 \u00d7 36 mm placement, including both 60-contact mezzanines. 12% less area than 37.5 \u00d7 36 mm; 17.5% less than 40 \u00d7 36 mm. No tracks, vias, zones or integrated schematic; all 120 mezzanine signal contacts remain unassigned. Native DRC: 0 physical violations / 383 unconnected items. Minimum courtyard gap approximately 0.010 mm; assembly tolerances unqualified. J4 body overhang is 0.65 mm, giving a drawn 33.65 \u00d7 36 mm board-plus-body envelope; full mating/insertion clearance is unverified.",
      "native": "../../../hardware/fpga-interface-study/dated/2026-09-26/size-and-pin-report/layout_v2/hardware/FPGA100T_33x36_Placement.kicad_pcb",
      "project": "../../../hardware/fpga-interface-study/dated/2026-09-26/size-and-pin-report/layout_v2/hardware/FPGA100T_33x36_Placement.kicad_pro",
      "zip": "../../../hardware/fpga-interface-study/dated/2026-09-26/size-and-pin-report/layout_v2/FPGA100T_33x36_Placement.zip",
      "svg": "../../../hardware/fpga-interface-study/dated/2026-09-26/size-and-pin-report/layout_v2/output/Compact_Placement.svg",
      "sha256": "e2aa37d7b569608729ed44e2d7946d30d108c2124e244e9707d49e6ca25df3de",
      "dimensions_mm": [
        33,
        36
      ],
      "expected": {
        "footprints": 128,
        "pads": 807,
        "segments": 0,
        "vias": 0,
        "zones": 0,
        "fpgaPads": 324,
        "copperLayers": 6,
        "nets": 265
      },
      "unconnected_items": 383,
      "manufacturing_ready": false
    }
  ],
  "default_board": "fpga50t"
}