{
  "result": "PASS",
  "date": "2026-09-27",
  "boardSha256": "2975050c28c89fc96bf781cf082bffffc84189e6720ce05c4200d8552ac298fc",
  "counts": {
    "canonicalPins": 752,
    "numberedPhysicalPads": 761,
    "allPhysicalPads": 801,
    "assigned": 650,
    "unassigned": 102,
    "cadNoConnect": 83,
    "groundRequired": 0,
    "groundingReview": 0,
    "groundCorrectionsAssigned": 6,
    "asicNetsAssigned": 116,
    "analogReservedContacts": 1,
    "fpgaUnassigned": 89,
    "mezzanineUnassigned": 3,
    "cableUnassigned": 8,
    "assignedNetOpenEndpoints": 0,
    "assignedNetConnectedEndpoints": 649,
    "missingAssignedConnections": 0
  },
  "checks": {
    "allNativeAndSchematicEndpointsAgree": true,
    "all116CandidateFPGAAssignmentsMatchCSV": true,
    "analogContactSeparatedFromFPGA": true,
    "allSixGroundPinsAssignedGND": true,
    "allNativeUnassignedEndpointsExplicitlyLabeled": true,
    "intentionalA13NCIdentified": true,
    "allNumberedPhysicalPadCoordinatesReadNatively": true,
    "noCADFilesModified": true
  },
  "routingAuditPending": false,
  "limitations": [
    "Assignments do not prove electrical compatibility, timing or hardware operation.",
    "Assigned-open is a net-level status; the selected pad may be locally connected.",
    "Physical maps show PCB top view, not mating-face numbering."
  ]
}