{ "schemaVersion": 1, "workDate": "2026-09-26", "boardSha256": "2975050c28c89fc96bf781cf082bffffc84189e6720ce05c4200d8552ac298fc", "scope": "Current 33 x 36 mm native ASIC117 assignment/copper snapshot; component purposes and connectivity refreshed.", "sourceFiles": [ { "path": "hardware/FPGA100T_33x36_Routing.kicad_pcb", "sha256": "2975050c28c89fc96bf781cf082bffffc84189e6720ce05c4200d8552ac298fc" }, { "path": "reports/FPGA100T_33x36_Routing.net", "sha256": "acb20c42453e423c7bd8b3e5e77b6c9787351a9c18173991fa6297b59c877ff6" }, { "path": "reports/component_manifest_resolved.json", "sha256": "05e0d225938a62e6180134a55b97beb41d5301d1108bf4f12cfac54525cf234d" }, { "path": "bringup/ASIC_Interface_Assignment.csv", "sha256": "51e1685a9cdd65170d6ce7682f20ffad2e5640abc78cf1ea1fc6b26a3cb2a521" } ], "statusLegend": { "required": { "label": "Keep function", "meaning": "Essential in the current circuit topology. Equivalent redesign is possible; this is not a claim that the exact manufacturer part is uniquely necessary." }, "architecture": { "label": "Depends on system choice", "meaning": "Required by the currently chosen rail, clock, boot or connector strategy. Remove or replace only with an explicit alternative architecture." }, "qualification": { "label": "Check before reducing", "meaning": "Supports supply quality, startup, signal quality or tuning. Its exact quantity/value is not proven minimal; removal requires relevant analysis or measurements." }, "nonessential": { "label": "Removal candidate", "meaning": "No current functional consumer was found for the feature. Deliberately remove/review its branch and recheck CAD, rather than simply depopulating series links." } }, "sources": [ { "id": "LOCAL", "title": "Current native PCB/XML assignments and inherited component-purpose review", "path": "Current PCB and FPGA100T_33x36_Routing.net; source hashes included", "basis": "Native assignment/geometry readback; manufacturer guidance remains separate from measured operation." }, { "id": "TI", "title": "TI TPS62135 datasheet", "url": "https://www.ti.com/lit/ds/symlink/tps62135.pdf", "locations": "Pin table p3; operating conditions p4; PG p9; soft start p15; distributed capacitance pp32–33; layout p36", "checked": "2026-09-26" }, { "id": "UG483", "title": "AMD 7 Series PCB Design Guide UG483", "url": "https://docs.amd.com/api/khub/documents/6L8DUUei7ZCE78qwQafC3A/content", "locations": "Table 2-2 pp15–16; capacitor specifications p19; placement p24; simulation pp36–38", "checked": "2026-09-26" }, { "id": "UG470", "title": "AMD 7 Series Configuration User Guide UG470", "url": "https://docs.amd.com/v/u/en-US/ug470_7Series_Config", "locations": "Table 2-4 configuration pin definitions; mode/PUDC_B ties; PROGRAM_B/INIT_B pulls; internal DONE pull-up", "localCopy": "FPGA_100T_CSG324/reports/boot_ug470.txt", "checked": "2026-09-26" }, { "id": "UG475", "title": "AMD 7 Series Packaging and Pinout UG475", "url": "https://docs.amd.com/api/khub/documents/kHyYQ6XzXnQwR2O~gaV~MQ/content", "locations": "Table 1-12, p26: unused DXP/DXN must be grounded", "checked": "2026-09-26" }, { "id": "DS181", "title": "AMD Artix 7 DC and AC Data Sheet DS181", "url": "https://docs.amd.com/api/khub/documents/iAkxxTOk96ANLJqYf2hgrQ/content", "locations": "Supply limits, sequencing and rail ramps", "checked": "2026-09-26" }, { "id": "MX", "title": "Macronix MX25U12835F 1.8 V flash datasheet", "url": "https://www.macronix.com/Lists/Datasheet/Attachments/8704/MX25U12835F,%201.8V,%20128Mb,%20v1.9.pdf", "locations": "8-SOP pinout; RESET#/SIO3 and WP#/SIO2 functions; startup and SPI modes", "checked": "2026-09-26" }, { "id": "ASE", "title": "Abracon ASE3 oscillator datasheet", "url": "https://abracon.com/Oscillators/ASE3series.pdf", "locations": "1.8 V operation, pin functions and bypass drawing", "checked": "2026-09-26" } ], "groups": [ { "id": "fpga", "title": "FPGA logic", "count": 1, "references": [ "U1" ] }, { "id": "power", "title": "Four power rails", "count": 38, "references": [ "C1", "C2", "C3", "C4", "C5", "C6", "C7", "C8", "C9", "C10", "C11", "C12", "C13", "C14", "C15", "C16", "C17", "C18", "L1", "L2", "L3", "L4", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9", "R10", "R11", "R122", "U2", "U3", "U4", "U5" ] }, { "id": "decoupling", "title": "FPGA supply decoupling", "count": 61, "references": [ "C20", "C21", "C22", "C23", "C24", "C25", "C26", "C27", "C28", "C29", "C30", "C31", "C32", "C33", "C34", "C35", "C36", "C37", "C40", "C41", "C42", "C43", "C44", "C45", "C46", "C50", "C51", "C52", "C53", "C54", "C55", "C56", "C57", "C58", "C59", "C60", "C61", "C62", "C63", "C64", "C65", "C66", "C67", "C68", "C69", "C70", "C71", "C72", "C73", "C74", "C75", "C76", "C77", "C78", "C79", "C80", "C81", "C82", "C90", "C91", "C92" ] }, { "id": "boot", "title": "Boot memory", "count": 9, "references": [ "C100", "C101", "R100", "R101", "R102", "R103", "R104", "R105", "U6" ] }, { "id": "clock", "title": "System clock", "count": 4, "references": [ "C102", "C103", "R119", "Y1" ] }, { "id": "configuration", "title": "Configuration and JTAG", "count": 9, "references": [ "R108", "R109", "R110", "R111", "R114", "R115", "R116", "R117", "R118" ] }, { "id": "connectors", "title": "External connections", "count": 3, "references": [ "J4", "J5", "J6" ] } ], "components": [ { "reference": "C1", "value": "47u 25V X5R", "mpn": "MSAST32MAB5476MPNDT1", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_input", "side": "Front", "status": "qualification", "shortRole": "Cable-entry bulk reservoir", "whyNeeded": "47 uF at the proposed 12 V cable entry supports slower input current changes before the individual converter input reservoirs.", "ifRemoved": "Reduces cable-entry energy reserve; depends on cable impedance, inrush and source behavior.", "reviewDecision": "Do not call this input protection. Retain pending a source/cable transient study; optimize jointly with the carrier, not by visual whitespace.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1210_3225Metric" }, { "reference": "C2", "value": "100n 100V X7R", "mpn": "GRM188R72A104KA35D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_input", "side": "Front", "status": "qualification", "shortRole": "Cable-entry high-frequency bypass", "whyNeeded": "100 nF from the cable input to GND bypasses faster voltage disturbance at entry.", "ifRemoved": "Changes entry-node high-frequency impedance.", "reviewDecision": "Review jointly with C1 and converter input loops. It does not clamp overvoltage.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C3", "value": "22u 25V X5R", "mpn": "MSAST31LBB5226MTNA01", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "required", "shortRole": "Converter input reservoir", "whyNeeded": "Local input reservoir from LINK_12V to GND next to U2. Supplies the converter switching loop.", "ifRemoved": "The local current loop relies on distant capacitors and cable inductance; input ripple and unstable startup become possible.", "reviewDecision": "Keep a qualified local input-capacitance function. Actual capacitance at 12 V, tolerance, temperature and aging must meet the input requirement.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1206_3216Metric" }, { "reference": "C4", "value": "100n 100V X7R", "mpn": "GRM188R72A104KA35D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "qualification", "shortRole": "High-frequency input bypass", "whyNeeded": "Small local 100 nF bypass across U2 input, alongside C3.", "ifRemoved": "Changes high-frequency input impedance. The larger capacitor may not behave identically at fast edges.", "reviewDecision": "A possible optimization only after checking switching-loop layout, impedance and EMI; not proven individually indispensable.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C5", "value": "22u 16V X5R", "mpn": "EMK212BBJ226MG-T", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "required", "shortRole": "Converter local output capacitor", "whyNeeded": "Local output reservoir and voltage-sense pickup for U2; the L/C output function works with L1.", "ifRemoved": "The output filter and sensed node lose their intended local capacitor; supply ripple and control behavior change.", "reviewDecision": "Keep a qualified local output capacitor. C5 and C9 remain upstream of R9 and R122 respectively.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCORE_REG_1V025", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C6", "value": "10n 50V X7R", "mpn": "GRM188R71H103KA01D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "qualification", "shortRole": "Soft-start timing capacitor", "whyNeeded": "10 nF from U2 SS/TR to GND controls the rail rise time. It is a timing choice, not the source of rail power.", "ifRemoved": "The converter uses its fast internal startup behavior; inrush and FPGA rail ramp/sequence change.", "reviewDecision": "Could be reduced or omitted only after measured startup remains within FPGA ramp and sequencing limits. Retain until those checks pass.", "sourceIds": [ "TI", "DS181", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "SS_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C7", "value": "22u 25V X5R", "mpn": "MSAST31LBB5226MTNA01", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "required", "shortRole": "Converter input reservoir", "whyNeeded": "Local input reservoir from LINK_12V to GND next to U3. Supplies the converter switching loop.", "ifRemoved": "The local current loop relies on distant capacitors and cable inductance; input ripple and unstable startup become possible.", "reviewDecision": "Keep a qualified local input-capacitance function. Actual capacitance at 12 V, tolerance, temperature and aging must meet the input requirement.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1206_3216Metric" }, { "reference": "C8", "value": "100n 100V X7R", "mpn": "GRM188R72A104KA35D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "qualification", "shortRole": "High-frequency input bypass", "whyNeeded": "Small local 100 nF bypass across U3 input, alongside C7.", "ifRemoved": "Changes high-frequency input impedance. The larger capacitor may not behave identically at fast edges.", "reviewDecision": "A possible optimization only after checking switching-loop layout, impedance and EMI; not proven individually indispensable.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C9", "value": "22u 16V X5R", "mpn": "EMK212BBJ226MG-T", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "required", "shortRole": "Converter local output capacitor", "whyNeeded": "Local output reservoir and voltage-sense pickup for U3; the L/C output function works with L2.", "ifRemoved": "The output filter and sensed node lose their intended local capacitor; supply ripple and control behavior change.", "reviewDecision": "Keep a qualified local output capacitor. C5 and C9 remain upstream of R9 and R122 respectively.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VAUX_REG_1V803", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C10", "value": "10n 50V X7R", "mpn": "GRM188R71H103KA01D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "qualification", "shortRole": "Soft-start timing capacitor", "whyNeeded": "10 nF from U3 SS/TR to GND controls the rail rise time. It is a timing choice, not the source of rail power.", "ifRemoved": "The converter uses its fast internal startup behavior; inrush and FPGA rail ramp/sequence change.", "reviewDecision": "Could be reduced or omitted only after measured startup remains within FPGA ramp and sequencing limits. Retain until those checks pass.", "sourceIds": [ "TI", "DS181", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "SS_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C11", "value": "22u 25V X5R", "mpn": "MSAST31LBB5226MTNA01", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_cfg", "side": "Front", "status": "required", "shortRole": "Converter input reservoir", "whyNeeded": "Local input reservoir from LINK_12V to GND next to U4. Supplies the converter switching loop.", "ifRemoved": "The local current loop relies on distant capacitors and cable inductance; input ripple and unstable startup become possible.", "reviewDecision": "Keep a qualified local input-capacitance function. Actual capacitance at 12 V, tolerance, temperature and aging must meet the input requirement.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1206_3216Metric" }, { "reference": "C12", "value": "100n 100V X7R", "mpn": "GRM188R72A104KA35D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_cfg", "side": "Front", "status": "qualification", "shortRole": "High-frequency input bypass", "whyNeeded": "Small local 100 nF bypass across U4 input, alongside C11.", "ifRemoved": "Changes high-frequency input impedance. The larger capacitor may not behave identically at fast edges.", "reviewDecision": "A possible optimization only after checking switching-loop layout, impedance and EMI; not proven individually indispensable.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C13", "value": "22u 16V X5R", "mpn": "EMK212BBJ226MG-T", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_cfg", "side": "Front", "status": "required", "shortRole": "Converter local output capacitor", "whyNeeded": "Local output reservoir and voltage-sense pickup for U4; the L/C output function works with L3.", "ifRemoved": "The output filter and sensed node lose their intended local capacitor; supply ripple and control behavior change.", "reviewDecision": "Keep a qualified local output capacitor. C5 and C9 remain upstream of R9 and R122 respectively.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C14", "value": "10n 50V X7R", "mpn": "GRM188R71H103KA01D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_cfg", "side": "Front", "status": "qualification", "shortRole": "Soft-start timing capacitor", "whyNeeded": "10 nF from U4 SS/TR to GND controls the rail rise time. It is a timing choice, not the source of rail power.", "ifRemoved": "The converter uses its fast internal startup behavior; inrush and FPGA rail ramp/sequence change.", "reviewDecision": "Could be reduced or omitted only after measured startup remains within FPGA ramp and sequencing limits. Retain until those checks pass.", "sourceIds": [ "TI", "DS181", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "SS_CFG", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C15", "value": "22u 25V X5R", "mpn": "MSAST31LBB5226MTNA01", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_asic", "side": "Back", "status": "required", "shortRole": "Converter input reservoir", "whyNeeded": "Local input reservoir from LINK_12V to GND next to U5. Supplies the converter switching loop.", "ifRemoved": "The local current loop relies on distant capacitors and cable inductance; input ripple and unstable startup become possible.", "reviewDecision": "Keep a qualified local input-capacitance function. Actual capacitance at 12 V, tolerance, temperature and aging must meet the input requirement.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1206_3216Metric" }, { "reference": "C16", "value": "100n 100V X7R", "mpn": "GRM188R72A104KA35D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_asic", "side": "Back", "status": "qualification", "shortRole": "High-frequency input bypass", "whyNeeded": "Small local 100 nF bypass across U5 input, alongside C15.", "ifRemoved": "Changes high-frequency input impedance. The larger capacitor may not behave identically at fast edges.", "reviewDecision": "A possible optimization only after checking switching-loop layout, impedance and EMI; not proven individually indispensable.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C17", "value": "22u 16V X5R", "mpn": "EMK212BBJ226MG-T", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_asic", "side": "Back", "status": "required", "shortRole": "Converter local output capacitor", "whyNeeded": "Local output reservoir and voltage-sense pickup for U5; the L/C output function works with L4.", "ifRemoved": "The output filter and sensed node lose their intended local capacitor; supply ripple and control behavior change.", "reviewDecision": "Keep a qualified local output capacitor. C5 and C9 remain upstream of R9 and R122 respectively.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C18", "value": "10n 50V X7R", "mpn": "GRM188R71H103KA01D", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_asic", "side": "Back", "status": "qualification", "shortRole": "Soft-start timing capacitor", "whyNeeded": "10 nF from U5 SS/TR to GND controls the rail rise time. It is a timing choice, not the source of rail power.", "ifRemoved": "The converter uses its fast internal startup behavior; inrush and FPGA rail ramp/sequence change.", "reviewDecision": "Could be reduced or omitted only after measured startup remains within FPGA ramp and sequencing limits. Retain until those checks pass.", "sourceIds": [ "TI", "DS181", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "SS_ASIC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C20", "value": "330u 2.5V POSCAP ESR9m@300kHz", "mpn": "ETPE330M9GB", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Bulk energy reserve", "whyNeeded": "330 microfarad polarized bulk capacitor on the FPGA side of R9. Supplies slower core-current changes; local small ceramic capacitors handle faster changes. The smaller manufacturer land pattern opens connector routing space.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Keep the bulk-capacitor function. ETPE330M9GB is the compact selection: 2.5 V, 105 C category maximum, ESR specified at 300 kHz and 20 C. Its model ESL reaches about 1.2 nH, so AMD decoupling-class equivalence, mounted PDN response, ripple and thermal performance still require qualification. Pad 1 is positive core; pad 2 is GND.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Panasonic_POSCAP_B2_Recommended" }, { "reference": "C21", "value": "100u 6.3V X5R", "mpn": "GRM32ER60J107ME20L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bram", "side": "Back", "status": "qualification", "shortRole": "Bulk energy reserve", "whyNeeded": "100u 6.3V X5R bulk energy reserve for FPGA block RAM between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence. The recorded part family is NRND; qualify an orderable alternative.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1210_3225Metric" }, { "reference": "C22", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C23", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C24", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C25", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C26", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C27", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C28", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C29", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C30", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C31", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C32", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C33", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C34", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C35", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_core", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA core between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C36", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bram", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA block RAM between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C37", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bram", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA block RAM between VCCINT_1V0 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C40", "value": "47u 6.3V X7R", "mpn": "GRM32ER70J476ME20L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_aux", "side": "Back", "status": "qualification", "shortRole": "Bulk energy reserve", "whyNeeded": "47u 6.3V X7R bulk energy reserve for FPGA auxiliary circuits between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1210_3225Metric" }, { "reference": "C41", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_aux", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for FPGA auxiliary circuits between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C42", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_aux", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for FPGA auxiliary circuits between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C43", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_aux", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA auxiliary circuits between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C44", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_aux", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA auxiliary circuits between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C45", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_aux", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA auxiliary circuits between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C46", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_aux", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for FPGA auxiliary circuits between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C50", "value": "47u 6.3V X7R", "mpn": "GRM32ER70J476ME20L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank0", "side": "Back", "status": "qualification", "shortRole": "Bulk energy reserve", "whyNeeded": "47u 6.3V X7R bulk energy reserve for configuration bank 0 between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1210_3225Metric" }, { "reference": "C51", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank14", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for configuration/user-I/O bank 14 between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C52", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank14", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for configuration/user-I/O bank 14 between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C53", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank14", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for configuration/user-I/O bank 14 between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C54", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank14", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for configuration/user-I/O bank 14 between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C55", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank14", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for configuration/user-I/O bank 14 between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C56", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank14", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for configuration/user-I/O bank 14 between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C57", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank16", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for link bank 16 between VCC_LINK_2V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C58", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank16", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for link bank 16 between VCC_LINK_2V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C59", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank16", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for link bank 16 between VCC_LINK_2V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C60", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank16", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for link bank 16 between VCC_LINK_2V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C61", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank16", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for link bank 16 between VCC_LINK_2V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C62", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank16", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for link bank 16 between VCC_LINK_2V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C63", "value": "47u 6.3V X7R", "mpn": "GRM32ER70J476ME20L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_cfg_bulk", "side": "Back", "status": "qualification", "shortRole": "Bulk energy reserve", "whyNeeded": "47u 6.3V X7R bulk energy reserve for link bank 16 between VCC_LINK_2V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1210_3225Metric" }, { "reference": "C64", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank15", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for ASIC-facing bank 15 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C65", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank15", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for ASIC-facing bank 15 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C66", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank15", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 15 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C67", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank15", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 15 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C68", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank15", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 15 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C69", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank15", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 15 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C70", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank34", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for ASIC-facing bank 34 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C71", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank34", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for ASIC-facing bank 34 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C72", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank34", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 34 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C73", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank34", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 34 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C74", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank34", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 34 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C75", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank34", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 34 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C76", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank35", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for ASIC-facing bank 35 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C77", "value": "4.7u 10V X7R", "mpn": "GRM21BR71A475KA73L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank35", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "4.7u 10V X7R local supply bypass for ASIC-facing bank 35 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0805_2012Metric" }, { "reference": "C78", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank35", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 35 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C79", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank35", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 35 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C80", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank35", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 35 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C81", "value": "470n 10V X7R", "mpn": "GRT155R71A474KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank35", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "470n 10V X7R local supply bypass for ASIC-facing bank 35 between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C82", "value": "47u 6.3V X7R", "mpn": "GRM32ER70J476ME20L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_asic_bulk", "side": "Front", "status": "qualification", "shortRole": "Bulk energy reserve", "whyNeeded": "47u 6.3V X7R bulk energy reserve for the three ASIC-facing banks between VCC_ASIC_1V5 and GND. Supplies short current pulses locally while the regulator and plane respond.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1210_3225Metric" }, { "reference": "C90", "value": "100n 16V X7R", "mpn": "GRT155R71C104KE01D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_xadc", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "100n 16V X7R local supply bypass for XADC analog supply between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond. The ADC-related supply still needs a defined electrical connection even when external temperature-diode sensing is unused.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Murata_GRT15_0402_Recommended" }, { "reference": "C91", "value": "1u 10V X7R", "mpn": "GRM188R71A105KA61D", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_xadc", "side": "Back", "status": "qualification", "shortRole": "Local supply bypass", "whyNeeded": "1u 10V X7R local supply bypass for XADC analog supply between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond. The ADC-related supply still needs a defined electrical connection even when external temperature-diode sensing is unused.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0603_1608Metric" }, { "reference": "C92", "value": "47u 6.3V X7R", "mpn": "GRM32ER70J476ME20L", "group": "decoupling", "groupLabel": "FPGA supply decoupling", "originalGroup": "decoupling_bank14_bulk", "side": "Back", "status": "qualification", "shortRole": "Bulk energy reserve", "whyNeeded": "47u 6.3V X7R bulk energy reserve for bank 14 between VCCAUX_1V8 and GND. Supplies short current pulses locally while the regulator and plane respond. Added when bank 14 and bank 16 were separated onto different voltages; it is not a duplicate on the 2.5 V rail.", "ifRemoved": "Less local stored charge and changed power-network impedance; may cause supply noise or transient failures. Removing one is not automatically safe or automatically fatal.", "reviewDecision": "Retain the documented decoupling baseline. This individual part is not proven to be the unique minimum; reduction requires equivalent impedance, effective capacitance and load-step evidence.", "sourceIds": [ "UG483", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_1210_3225Metric" }, { "reference": "C100", "value": "100n", "mpn": "GRM155R71C104KA88D", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "required", "shortRole": "Flash local supply bypass", "whyNeeded": "100 nF between U6 VCC and GND supports local flash switching current.", "ifRemoved": "Removes the smallest local flash reservoir; remote rail capacitance does not guarantee an equivalent short current loop.", "reviewDecision": "The exact capacitor order code is selected. Keep its bypass function; effective capacitance and the mounted power network still need qualification.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0402_1005Metric" }, { "reference": "C101", "value": "1u 16V X5R", "mpn": "GRM155R61C105KA12D", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "qualification", "shortRole": "Flash local bulk reservoir", "whyNeeded": "1 uF supplements C100 at the flash supply.", "ifRemoved": "Less local reserve; flash current transients must then be met by C100 and the rail network.", "reviewDecision": "Potential reduction only after supply-noise and flash power-cycle tests.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0402_1005Metric" }, { "reference": "C102", "value": "10n", "mpn": "GRM155R71C103KA01D", "group": "clock", "groupLabel": "System clock", "originalGroup": "Reference clock", "side": "Front", "status": "required", "shortRole": "Oscillator local supply bypass", "whyNeeded": "10 nF adjacent to Y1 VDD/GND follows the oscillator bypass arrangement in the selected-part documentation.", "ifRemoved": "Removes its intended shortest bypass path.", "reviewDecision": "Keep local bypass when Y1 is fitted. ASE3 recommends 10 nF, but its note incorrectly says pins 7/14; the actual four-pin table is VDD=4 and GND=2. Use that verified mapping.", "sourceIds": [ "ASE", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0402_1005Metric" }, { "reference": "C103", "value": "100n", "mpn": "GRM155R71C104KA88D", "group": "clock", "groupLabel": "System clock", "originalGroup": "Reference clock", "side": "Front", "status": "qualification", "shortRole": "Additional oscillator bypass", "whyNeeded": "100 nF supplements Y1 local supply bypass C102.", "ifRemoved": "Less local supply filtering; consequence depends on supply impedance and clock sensitivity.", "reviewDecision": "Can be optimized after clock jitter/supply-noise evidence; do not claim two bypass parts are universally mandatory.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Capacitor_SMD__C_0402_1005Metric" }, { "reference": "J4", "value": "CUSTOM POWER + JTAG / DATA TBD", "mpn": "467651001", "group": "connectors", "groupLabel": "External connections", "originalGroup": "Custom shared cable / power and JTAG", "side": "Front", "status": "architecture", "shortRole": "Shared power / JTAG / future data cable", "whyNeeded": "One custom Type-D connector replaces separate power and debug connectors and reserves contacts for four data pairs.", "ifRemoved": "The selected power-entry and external programming access disappear.", "reviewDecision": "Keep one system connector. Exact cable pinout, protected source and receiver design must be qualified; this custom 12 V wiring is not HDMI compatible.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "JTAG_TMS", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "3", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved cable-data contact; link implementation is deferred. Custom electrical interface, not HDMI compatible." }, { "pin": "4", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "5", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved cable-data contact; link implementation is deferred. Custom electrical interface, not HDMI compatible." }, { "pin": "6", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved cable-data contact; link implementation is deferred. Custom electrical interface, not HDMI compatible." }, { "pin": "7", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "8", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved cable-data contact; link implementation is deferred. Custom electrical interface, not HDMI compatible." }, { "pin": "9", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved cable-data contact; link implementation is deferred. Custom electrical interface, not HDMI compatible." }, { "pin": "10", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "11", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved cable-data contact; link implementation is deferred. Custom electrical interface, not HDMI compatible." }, { "pin": "12", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved cable-data contact; link implementation is deferred. Custom electrical interface, not HDMI compatible." }, { "pin": "13", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "14", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved cable-data contact; link implementation is deferred. Custom electrical interface, not HDMI compatible." }, { "pin": "15", "function": "", "net": "JTAG_TDI", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "16", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "17", "function": "", "net": "JTAG_TCK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "18", "function": "", "net": "JTAG_TDO", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "19", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "SH", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:LinkPort__MicroHDMI_46765_1xxx" }, { "reference": "J5", "value": "QSH-030-01-L-D-A", "mpn": "QSH-030-01-L-D-A", "group": "connectors", "groupLabel": "External connections", "originalGroup": "ASIC mezzanine", "side": "Front", "status": "architecture", "shortRole": "60-contact ASIC mezzanine", "whyNeeded": "One half of the chosen two-connector ASIC interface; together J5/J6 offer 120 numbered signal contacts plus ground-blade lands.", "ifRemoved": "The proposed 117-contact interface no longer fits in the remaining 60 contacts.", "reviewDecision": "Keep both for the selected 2 x 60 interface. There are 116 candidate digital FPGA connections, one AC_IN analog contact reserved for the routing/ASIC side, and three spare contacts. Electrical compatibility, connector mating and timing are not yet approved.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "ASIC1_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "2", "function": "", "net": "ASIC1_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "3", "function": "", "net": "ASIC1_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "4", "function": "", "net": "ASIC1_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "5", "function": "", "net": "ASIC1_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "6", "function": "", "net": "ASIC1_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "7", "function": "", "net": "ASIC1_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "8", "function": "", "net": "ASIC1_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "9", "function": "", "net": "ASIC1_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "10", "function": "", "net": "ASIC1_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "11", "function": "", "net": "ASIC1_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "12", "function": "", "net": "ASIC2_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "13", "function": "", "net": "ASIC2_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "14", "function": "", "net": "ASIC2_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "15", "function": "", "net": "ASIC2_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "16", "function": "", "net": "ASIC2_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "17", "function": "", "net": "ASIC2_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "18", "function": "", "net": "ASIC2_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "19", "function": "", "net": "ASIC2_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "20", "function": "", "net": "ASIC2_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "21", "function": "", "net": "ASIC2_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "22", "function": "", "net": "ASIC2_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "23", "function": "", "net": "ASIC3_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "24", "function": "", "net": "ASIC3_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "25", "function": "", "net": "ASIC3_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "26", "function": "", "net": "ASIC3_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "27", "function": "", "net": "ASIC3_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "28", "function": "", "net": "ASIC3_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "29", "function": "", "net": "ASIC3_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "30", "function": "", "net": "ASIC3_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "31", "function": "", "net": "ASIC3_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "32", "function": "", "net": "ASIC3_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "33", "function": "", "net": "ASIC3_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "34", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved mezzanine contact, intentionally left unassigned for now. The 116 candidate digital contacts and one external analog contact are allocated elsewhere; mating orientation and ground returns remain to be verified." }, { "pin": "35", "function": "", "net": "ASIC4_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "36", "function": "", "net": "ASIC4_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "37", "function": "", "net": "ASIC4_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "38", "function": "", "net": "ASIC4_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "39", "function": "", "net": "ASIC4_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "40", "function": "", "net": "ASIC4_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "41", "function": "", "net": "ASIC4_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "42", "function": "", "net": "ASIC4_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "43", "function": "", "net": "ASIC4_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "44", "function": "", "net": "ASIC4_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "45", "function": "", "net": "CHIP_RESET_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "46", "function": "", "net": "AC_IN_ANALOG_RESERVED", "status": "analog reserved — external source required; no FPGA connection", "note": "AC_IN is an analog 0–1.5 V ASIC input. This contact is reserved for a source on the routing/ASIC side; it has no FPGA GPIO connection. The source circuit, return/reference and loading still require design. A single named pad with no DRC airwire is not a working analog source." }, { "pin": "47", "function": "", "net": "IMP_TST_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified. IMP_TST is provisionally treated as a 0/1.5 V digital output; inactive polarity and timing remain unverified." }, { "pin": "48", "function": "", "net": "FE_RESET_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "49", "function": "", "net": "SPI_LATCH_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "50", "function": "", "net": "STIM_CLK_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "51", "function": "", "net": "STIM_START_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "52", "function": "", "net": "STIM_EN_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "53", "function": "", "net": "STIM_CHB_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "54", "function": "", "net": "BOARD1_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "55", "function": "", "net": "BOARD2_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "56", "function": "", "net": "BOARD3_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "57", "function": "", "net": "BOARD4_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "58", "function": "", "net": "BOARD1_SPI_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "59", "function": "", "net": "BOARD2_SPI_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "60", "function": "", "net": "BOARD3_SPI_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "Mezzanine:Samtec_QSH-030-01-L-D-A" }, { "reference": "J6", "value": "QSH-030-01-L-D-A", "mpn": "QSH-030-01-L-D-A", "group": "connectors", "groupLabel": "External connections", "originalGroup": "ASIC mezzanine", "side": "Front", "status": "architecture", "shortRole": "60-contact ASIC mezzanine", "whyNeeded": "One half of the chosen two-connector ASIC interface; together J5/J6 offer 120 numbered signal contacts plus ground-blade lands.", "ifRemoved": "The proposed 117-contact interface no longer fits in the remaining 60 contacts.", "reviewDecision": "Keep both for the selected 2 x 60 interface. There are 116 candidate digital FPGA connections, one AC_IN analog contact reserved for the routing/ASIC side, and three spare contacts. Electrical compatibility, connector mating and timing are not yet approved.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "ASIC5_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "2", "function": "", "net": "ASIC5_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "3", "function": "", "net": "ASIC5_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "4", "function": "", "net": "ASIC5_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "5", "function": "", "net": "ASIC5_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "6", "function": "", "net": "ASIC5_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "7", "function": "", "net": "ASIC5_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "8", "function": "", "net": "ASIC5_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "9", "function": "", "net": "ASIC5_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "10", "function": "", "net": "ASIC5_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "11", "function": "", "net": "ASIC5_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "12", "function": "", "net": "ASIC6_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "13", "function": "", "net": "ASIC6_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "14", "function": "", "net": "ASIC6_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "15", "function": "", "net": "ASIC6_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "16", "function": "", "net": "ASIC6_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "17", "function": "", "net": "ASIC6_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "18", "function": "", "net": "ASIC6_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "19", "function": "", "net": "ASIC6_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "20", "function": "", "net": "ASIC6_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "21", "function": "", "net": "ASIC6_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "22", "function": "", "net": "ASIC6_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "23", "function": "", "net": "ASIC7_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "24", "function": "", "net": "ASIC7_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "25", "function": "", "net": "ASIC7_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "26", "function": "", "net": "ASIC7_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "27", "function": "", "net": "ASIC7_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "28", "function": "", "net": "ASIC7_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "29", "function": "", "net": "ASIC7_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "30", "function": "", "net": "ASIC7_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "31", "function": "", "net": "ASIC7_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "32", "function": "", "net": "ASIC7_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "33", "function": "", "net": "ASIC7_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "34", "function": "", "net": "ASIC8_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "35", "function": "", "net": "ASIC8_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "36", "function": "", "net": "ASIC8_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "37", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved mezzanine contact, intentionally left unassigned for now. The 116 candidate digital contacts and one external analog contact are allocated elsewhere; mating orientation and ground returns remain to be verified." }, { "pin": "38", "function": "", "net": "ASIC8_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "39", "function": "", "net": "ASIC8_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "40", "function": "", "net": "ASIC8_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "41", "function": "", "net": "ASIC8_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "42", "function": "", "net": "ASIC8_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "43", "function": "", "net": "ASIC8_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "44", "function": "", "net": "ASIC8_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "45", "function": "", "net": "BOARD4_SPI_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "46", "function": "", "net": "STIM_CHIP1_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "47", "function": "", "net": "STIM_CHIP1_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "48", "function": "", "net": "STIM_CHIP2_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "49", "function": "", "net": "STIM_CHIP2_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "50", "function": "", "net": "STIM_CHIP3_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "51", "function": "", "net": "STIM_CHIP3_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "52", "function": "", "net": "STIM_CHIP4_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "53", "function": "", "net": "STIM_CHIP4_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "54", "function": "", "net": "NONSTIM_BOARD1_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "55", "function": "", "net": "NONSTIM_BOARD1_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "56", "function": "", "net": "NONSTIM_BOARD2_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "57", "function": "", "net": "NONSTIM_BOARD2_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "58", "function": "", "net": "ASIC8_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "59", "function": "", "net": "", "status": "reserved — interface implementation required", "note": "Reserved mezzanine contact, intentionally left unassigned for now. The 116 candidate digital contacts and one external analog contact are allocated elsewhere; mating orientation and ground returns remain to be verified." }, { "pin": "60", "function": "", "net": "ASIC4_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "Mezzanine:Samtec_QSH-030-01-L-D-A" }, { "reference": "L1", "value": "1uH 5.4A Isat30%", "mpn": "XFL4020-102MEC", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "required", "shortRole": "Buck energy-storage inductor", "whyNeeded": "Carries U2 switched current to its local output capacitor C5; this is part of the conversion path.", "ifRemoved": "Open circuit cuts power to the rail; replacing with a short exposes the load to switching pulses.", "reviewDecision": "Keep the function; verify inductance under load, saturation, heating and selected footprint.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "SW_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "VCORE_REG_1V025", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:PowerDraft__L_Coilcraft_XFL4020" }, { "reference": "L2", "value": "1uH 5.4A Isat30%", "mpn": "XFL4020-102MEC", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "required", "shortRole": "Buck energy-storage inductor", "whyNeeded": "Carries U3 switched current to its local output capacitor C9; this is part of the conversion path.", "ifRemoved": "Open circuit cuts power to the rail; replacing with a short exposes the load to switching pulses.", "reviewDecision": "Keep the function; verify inductance under load, saturation, heating and selected footprint.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "SW_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "VAUX_REG_1V803", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:PowerDraft__L_Coilcraft_XFL4020" }, { "reference": "L3", "value": "1uH 5.4A Isat30%", "mpn": "XFL4020-102MEC", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_cfg", "side": "Front", "status": "required", "shortRole": "Buck energy-storage inductor", "whyNeeded": "Carries U4 switched current to its local output capacitor C13; this is part of the conversion path.", "ifRemoved": "Open circuit cuts power to the rail; replacing with a short exposes the load to switching pulses.", "reviewDecision": "Keep the function; verify inductance under load, saturation, heating and selected footprint.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "SW_CFG", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:PowerDraft__L_Coilcraft_XFL4020" }, { "reference": "L4", "value": "1uH 5.4A Isat30%", "mpn": "XFL4020-102MEC", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_asic", "side": "Back", "status": "required", "shortRole": "Buck energy-storage inductor", "whyNeeded": "Carries U5 switched current to its local output capacitor C17; this is part of the conversion path.", "ifRemoved": "Open circuit cuts power to the rail; replacing with a short exposes the load to switching pulses.", "reviewDecision": "Keep the function; verify inductance under load, saturation, heating and selected footprint.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "SW_ASIC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:PowerDraft__L_Coilcraft_XFL4020" }, { "reference": "R1", "value": "32.4k 0.1%", "mpn": "TNPW060332K4BEEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "required", "shortRole": "Core / block ram feedback divider", "whyNeeded": "The upper resistor of U2 output-setting divider; R1/R2 determines the chosen regulated voltage.", "ifRemoved": "The intended feedback ratio is lost; the rail may be wrong, too low or driven high.", "reviewDecision": "Keep both divider functions with required tolerance; never treat these as optional bias resistors.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCORE_REG_1V025", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FB_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R2", "value": "69.8k 0.1%", "mpn": "TNPW060369K8BEEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "required", "shortRole": "Core / block ram feedback divider", "whyNeeded": "The lower resistor of U2 output-setting divider; R1/R2 determines the chosen regulated voltage.", "ifRemoved": "The intended feedback ratio is lost; the rail may be wrong, too low or driven high.", "reviewDecision": "Keep both divider functions with required tolerance; never treat these as optional bias resistors.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "FB_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R3", "value": "110k 0.1%", "mpn": "TNPW0603110KBEEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "required", "shortRole": "Auxiliary / configuration feedback divider", "whyNeeded": "The upper resistor of U3 output-setting divider; R3/R4 determines the chosen regulated voltage.", "ifRemoved": "The intended feedback ratio is lost; the rail may be wrong, too low or driven high.", "reviewDecision": "Keep both divider functions with required tolerance; never treat these as optional bias resistors.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VAUX_REG_1V803", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FB_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R4", "value": "69.8k 0.1%", "mpn": "TNPW060369K8BEEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "required", "shortRole": "Auxiliary / configuration feedback divider", "whyNeeded": "The lower resistor of U3 output-setting divider; R3/R4 determines the chosen regulated voltage.", "ifRemoved": "The intended feedback ratio is lost; the rail may be wrong, too low or driven high.", "reviewDecision": "Keep both divider functions with required tolerance; never treat these as optional bias resistors.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "FB_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R5", "value": "180k 0.1%", "mpn": "TNPW0603180KBEEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_cfg", "side": "Front", "status": "required", "shortRole": "2.5 v link bank feedback divider", "whyNeeded": "The upper resistor of U4 output-setting divider; R5/R6 determines the chosen regulated voltage.", "ifRemoved": "The intended feedback ratio is lost; the rail may be wrong, too low or driven high.", "reviewDecision": "Keep both divider functions with required tolerance; never treat these as optional bias resistors.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FB_CFG", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R6", "value": "69.8k 0.1%", "mpn": "TNPW060369K8BEEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_cfg", "side": "Front", "status": "required", "shortRole": "2.5 v link bank feedback divider", "whyNeeded": "The lower resistor of U4 output-setting divider; R5/R6 determines the chosen regulated voltage.", "ifRemoved": "The intended feedback ratio is lost; the rail may be wrong, too low or driven high.", "reviewDecision": "Keep both divider functions with required tolerance; never treat these as optional bias resistors.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "FB_CFG", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R7", "value": "80.6k 0.1%", "mpn": "TNPW060380K6BEEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_asic", "side": "Back", "status": "required", "shortRole": "1.5 v asic-facing banks feedback divider", "whyNeeded": "The upper resistor of U5 output-setting divider; R7/R8 determines the chosen regulated voltage.", "ifRemoved": "The intended feedback ratio is lost; the rail may be wrong, too low or driven high.", "reviewDecision": "Keep both divider functions with required tolerance; never treat these as optional bias resistors.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FB_ASIC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R8", "value": "69.8k 0.1%", "mpn": "TNPW060369K8BEEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_asic", "side": "Back", "status": "required", "shortRole": "1.5 v asic-facing banks feedback divider", "whyNeeded": "The lower resistor of U5 output-setting divider; R7/R8 determines the chosen regulated voltage.", "ifRemoved": "The intended feedback ratio is lost; the rail may be wrong, too low or driven high.", "reviewDecision": "Keep both divider functions with required tolerance; never treat these as optional bias resistors.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "FB_ASIC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R9", "value": "12m 1% 1W", "mpn": "WSLP1206R0120FEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "required", "shortRole": "Distributed-capacitance isolation", "whyNeeded": "12 milliohm series element between VCORE_REG_1V025 and VCCINT_1V0; local sensing remains upstream and distributed FPGA capacitors downstream. Reduces DC loss relative to the earlier 15 milliohm selection while retaining the reviewed isolation margin.", "ifRemoved": "Removing it opens the rail; shorting it defeats the deliberately separated local and distributed capacitor networks.", "reviewDecision": "Retain for this topology. Replacing it requires a demonstrated alternative series impedance and a full DC-drop/stability review.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCORE_REG_1V025", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_1206_3216Metric" }, { "reference": "R10", "value": "100k", "mpn": "CRCW0603100KFKEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "required", "shortRole": "Power-up sequencing pull-up", "whyNeeded": "Pulls PG_CORE high when U2 releases its open-drain power-good output; that signal enables U3.", "ifRemoved": "The downstream enable no longer receives its designed high level.", "reviewDecision": "Keep while this sequencing chain is used; startup and unplug waveforms still need checking.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "PG_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R11", "value": "100k", "mpn": "CRCW0603100KFKEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "required", "shortRole": "Power-up sequencing pull-up", "whyNeeded": "Pulls PG_AUX high when U3 releases its open-drain power-good output; that signal enables U4 and U5.", "ifRemoved": "The downstream enable no longer receives its designed high level.", "reviewDecision": "Keep while this sequencing chain is used; startup and unplug waveforms still need checking.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "PG_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0603_1608Metric" }, { "reference": "R100", "value": "2.4k", "mpn": "CRCW04022K40FKED", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "required", "shortRole": "Flash chip-select pull-up", "whyNeeded": "Holds FLASH_CS_B high while FPGA control is high impedance, preventing accidental selection.", "ifRemoved": "Flash chip select loses its external defined idle-high state during startup.", "reviewDecision": "Keep for the selected SPI boot interface.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FLASH_CS_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R101", "value": "4.7k", "mpn": "CRCW04024K70FKED", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "architecture", "shortRole": "Flash WP / DQ2 default high", "whyNeeded": "Holds flash U6.3 WP#/SIO2 high for the selected single-bit SPI boot. The optional FPGA DQ2 path and R106 are removed; this resistor still supplies the required defined flash input level.", "ifRemoved": "The flash write-protect/data pin may lose its defined default level when FPGA outputs are undriven.", "reviewDecision": "Keep the flash WP# pull-up. The image and programmer must use SPI x1; quad boot is not wired in this revision.", "sourceIds": [ "MX", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FLASH_DQ2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R102", "value": "4.7k", "mpn": "CRCW04024K70FKED", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "architecture", "shortRole": "Flash RESET / DQ3 default high", "whyNeeded": "Pulls U6 RESET#/SIO3 high so the selected flash is not unintentionally held in reset.", "ifRemoved": "The reset/data pin may lose its defined default level before configuration.", "reviewDecision": "Keep for this exact flash part and mode; it is RESET#, not a generic HOLD# pin.", "sourceIds": [ "MX", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FLASH_DQ3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R103", "value": "33", "mpn": "CRCW040233R0FKED", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "qualification", "shortRole": "Flash clock source damping", "whyNeeded": "33 ohm series element reduces fast-edge ringing in this saved signal path; its actual value depends on driver, trace/cable and load.", "ifRemoved": "If simply depopulated, the signal path is broken. Replacing it with copper removes the damping.", "reviewDecision": "Tune or replace by a direct route only after signal-integrity evidence. The existing 33 ohm value is a draft value, not a measured optimum.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "FPGA_CCLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FLASH_SCLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R104", "value": "0", "mpn": "CRCW04020000Z0ED", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "qualification", "shortRole": "Zero-ohm flash signal link", "whyNeeded": "Provides an editable series location in the DQ0 path. Its fitted 0 ohm value is electrically a link.", "ifRemoved": "Depopulating it breaks the signal; a deliberate trace replacement keeps connectivity.", "reviewDecision": "Footprint-removal candidate after signal-integrity/boot-mode review; do not confuse removing the component with leaving an open circuit.", "sourceIds": [ "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "FPGA_CFG_DQ0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FLASH_DQ0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R105", "value": "33", "mpn": "CRCW040233R0FKED", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "qualification", "shortRole": "Flash data source damping", "whyNeeded": "33 ohm series element reduces fast-edge ringing in this saved signal path; its actual value depends on driver, trace/cable and load.", "ifRemoved": "If simply depopulated, the signal path is broken. Replacing it with copper removes the damping.", "reviewDecision": "Tune or replace by a direct route only after signal-integrity evidence. The existing 33 ohm value is a draft value, not a measured optimum.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "FPGA_CFG_DQ1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FLASH_DQ1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R108", "value": "4.7k", "mpn": "CRCW04024K70FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Front", "status": "required", "shortRole": "PROGRAM_B pull-up", "whyNeeded": "4.7 kilohm to the 1.8 V configuration rail gives PROGRAM_B the specified released/high state.", "ifRemoved": "Configuration reset/initialization behavior can become undefined or stall.", "reviewDecision": "Keep the pull-up function required for this configuration scheme.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FPGA_PROGRAM_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R109", "value": "4.7k", "mpn": "CRCW04024K70FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Front", "status": "required", "shortRole": "INIT_B pull-up", "whyNeeded": "4.7 kilohm to the 1.8 V configuration rail gives INIT_B the specified released/high state.", "ifRemoved": "Configuration reset/initialization behavior can become undefined or stall.", "reviewDecision": "Keep the pull-up function required for this configuration scheme.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FPGA_INIT_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R110", "value": "4.7k", "mpn": "CRCW04024K70FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Front", "status": "qualification", "shortRole": "Additional DONE pull-up", "whyNeeded": "4.7 kilohm supplements the FPGA internal DONE pull-up. The current DONE net has no external monitor or LED.", "ifRemoved": "DONE retains its internal pull-up; whether its rise is acceptable depends on configuration settings and loading.", "reviewDecision": "A removal candidate after confirming DonePipe/startup settings, leakage and waveform. Do not state that every external DONE pull-up is mandatory.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "FPGA_DONE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R111", "value": "1k", "mpn": "CRCW04021K00FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Front", "status": "architecture", "shortRole": "Configuration strap M0", "whyNeeded": "1 kilohm sets M0 to 1.8 V / high. M[2:0]=001 chooses SPI; PUDC_B high disables configuration-time user-I/O pull-ups.", "ifRemoved": "The deliberately fixed configuration input loses its chosen strap unless replaced by a direct connection.", "reviewDecision": "The stable logic level is needed; the separate resistor is not inherently needed. UG470 permits a direct rail/GND tie, so a later revision can replace it with copper after the pin and configuration choice is frozen.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "CFG_M0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R114", "value": "1k", "mpn": "CRCW04021K00FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Front", "status": "architecture", "shortRole": "Configuration strap PUDC_B", "whyNeeded": "1 kilohm sets PUDC_B to 1.8 V / high. M[2:0]=001 chooses SPI; PUDC_B high disables configuration-time user-I/O pull-ups.", "ifRemoved": "The deliberately fixed configuration input loses its chosen strap unless replaced by a direct connection.", "reviewDecision": "The stable logic level is needed; the separate resistor is not inherently needed. UG470 permits a direct rail/GND tie, so a later revision can replace it with copper after the pin and configuration choice is frozen.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "CFG_PUDC_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R115", "value": "10k", "mpn": "CRCW040210K0FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Front", "status": "qualification", "shortRole": "JTAG TMS external idle bias", "whyNeeded": "10 kilohm to 1.8 V provides a weak external high level at JTAG TMS when the cable is undriven.", "ifRemoved": "External idle bias disappears; behavior then depends on device internal pulls and the actual adapter/cable.", "reviewDecision": "Review with the programming-interface contract. The current direct, single-FPGA connection does not prove that all three extra resistors are mandatory.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "JTAG_TMS", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R116", "value": "10k", "mpn": "CRCW040210K0FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Front", "status": "qualification", "shortRole": "JTAG TDI external idle bias", "whyNeeded": "10 kilohm to 1.8 V provides a weak external high level at JTAG TDI when the cable is undriven.", "ifRemoved": "External idle bias disappears; behavior then depends on device internal pulls and the actual adapter/cable.", "reviewDecision": "Review with the programming-interface contract. The current direct, single-FPGA connection does not prove that all three extra resistors are mandatory.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "JTAG_TDI", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R117", "value": "10k", "mpn": "CRCW040210K0FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Front", "status": "qualification", "shortRole": "JTAG TCK external idle bias", "whyNeeded": "10 kilohm to 1.8 V provides a weak external high level at JTAG TCK when the cable is undriven.", "ifRemoved": "External idle bias disappears; behavior then depends on device internal pulls and the actual adapter/cable.", "reviewDecision": "Review with the programming-interface contract. The current direct, single-FPGA connection does not prove that all three extra resistors are mandatory.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "JTAG_TCK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R118", "value": "33", "mpn": "CRCW040233R0FKED", "group": "configuration", "groupLabel": "Configuration and JTAG", "originalGroup": "Programming JTAG", "side": "Back", "status": "qualification", "shortRole": "JTAG TDO source damping", "whyNeeded": "33 ohm series element reduces fast-edge ringing in this saved signal path; its actual value depends on driver, trace/cable and load.", "ifRemoved": "If simply depopulated, the signal path is broken. Replacing it with copper removes the damping.", "reviewDecision": "Tune or replace by a direct route only after signal-integrity evidence. The existing 33 ohm value is a draft value, not a measured optimum.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "FPGA_TDO", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "JTAG_TDO", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R119", "value": "33", "mpn": "CRCW040233R0FKED", "group": "clock", "groupLabel": "System clock", "originalGroup": "Reference clock", "side": "Front", "status": "qualification", "shortRole": "Oscillator output damping", "whyNeeded": "33 ohm series element reduces fast-edge ringing in this saved signal path; its actual value depends on driver, trace/cable and load.", "ifRemoved": "If simply depopulated, the signal path is broken. Replacing it with copper removes the damping.", "reviewDecision": "Tune or replace by a direct route only after signal-integrity evidence. The existing 33 ohm value is a draft value, not a measured optimum.", "sourceIds": [ "UG470", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "OSC_32M_RAW", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "CLK_32MHZ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_0402_1005Metric" }, { "reference": "R122", "value": "15m 1% 1W", "mpn": "WSLP1206R0150FEA", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux_bulk_isolation", "side": "Back", "status": "required", "shortRole": "Distributed-capacitance isolation", "whyNeeded": "15 milliohm series element between VAUX_REG_1V803 and VCCAUX_1V8; local sensing remains upstream, distributed FPGA capacitors downstream.", "ifRemoved": "Removing it opens the rail; shorting it defeats the deliberately separated local and distributed capacitor networks.", "reviewDecision": "Retain for this topology. Replacing it requires a demonstrated alternative series impedance and a full DC-drop/stability review.", "sourceIds": [ "TI", "LOCAL" ], "pins": [ { "pin": "1", "function": "", "net": "VAUX_REG_1V803", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Resistor_SMD__R_1206_3216Metric" }, { "reference": "U1", "value": "XC7A100T-1CSG324I", "mpn": "XC7A100T-1CSG324I", "group": "fpga", "groupLabel": "FPGA logic", "originalGroup": "FPGA", "side": "Front", "status": "required", "shortRole": "Acquire, time and package ASIC data", "whyNeeded": "The XC7A100T is the board logic device. Its planned firmware captures the ASIC interface, supplies control/clock signals and sends data downstream.", "ifRemoved": "There is no FPGA function.", "reviewDecision": "Keep XC7A100T-1CSG324I. The 116 candidate digital ASIC balls are assigned; AC_IN is external analog. Eighty-one balls are intentionally NC and eight future-link balls remain reserved. Clock placement, external timing and powered operation still require validation.", "sourceIds": [ "DS181", "LOCAL" ], "pins": [ { "pin": "A1", "function": "IO_L9N_T1_DQS_AD7N_35", "net": "ASIC2_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A2", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "A3", "function": "IO_L8N_T1_AD14N_35", "net": "ASIC2_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A4", "function": "IO_L8P_T1_AD14P_35", "net": "ASIC4_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A5", "function": "IO_L3N_T0_DQS_AD5N_35", "net": "ASIC4_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A6", "function": "IO_L3P_T0_DQS_AD5P_35", "net": "ASIC4_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A7", "function": "VCCO_35", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "A8", "function": "IO_L12N_T1_MRCC_16", "net": "", "status": "reserved — interface implementation required", "note": "No functional net is assigned. The 116 candidate digital ASIC signals have other package balls. This ball is not automatically an approved spare; bank voltage and special functions still matter." }, { "pin": "A9", "function": "IO_L14N_T2_SRCC_16", "net": "", "status": "reserved — interface implementation required", "note": "No functional net is assigned. The 116 candidate digital ASIC signals have other package balls. This ball is not automatically an approved spare; bank voltage and special functions still matter." }, { "pin": "A10", "function": "IO_L14P_T2_SRCC_16", "net": "", "status": "reserved — interface implementation required", "note": "No functional net is assigned. The 116 candidate digital ASIC signals have other package balls. This ball is not automatically an approved spare; bank voltage and special functions still matter." }, { "pin": "A11", "function": "IO_L4N_T0_15", "net": "SPI_LATCH_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A12", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "A13", "function": "IO_L9P_T1_DQS_AD3P_15", "net": "", "status": "intentional no-connect", "note": "AC_IN analog is provided on carrier; no FPGA connection permitted under current design. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "A14", "function": "IO_L9N_T1_DQS_AD3N_15", "net": "BOARD2_SPI_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A15", "function": "IO_L8P_T1_AD10P_15", "net": "STIM_EN_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A16", "function": "IO_L8N_T1_AD10N_15", "net": "BOARD3_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "A17", "function": "VCCO_15", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "A18", "function": "IO_L10N_T1_AD11N_15", "net": "BOARD3_SPI_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B1", "function": "IO_L9P_T1_DQS_AD7P_35", "net": "ASIC1_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B2", "function": "IO_L10N_T1_AD15N_35", "net": "ASIC2_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B3", "function": "IO_L10P_T1_AD15P_35", "net": "ASIC2_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B4", "function": "IO_L7N_T1_AD6N_35", "net": "ASIC2_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B5", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "B6", "function": "IO_L2N_T0_AD12N_35", "net": "ASIC4_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B7", "function": "IO_L2P_T0_AD12P_35", "net": "ASIC4_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B8", "function": "IO_L12P_T1_MRCC_16", "net": "", "status": "reserved — interface implementation required", "note": "No functional net is assigned. The 116 candidate digital ASIC signals have other package balls. This ball is not automatically an approved spare; bank voltage and special functions still matter." }, { "pin": "B9", "function": "IO_L11N_T1_SRCC_16", "net": "", "status": "reserved — interface implementation required", "note": "No functional net is assigned. The 116 candidate digital ASIC signals have other package balls. This ball is not automatically an approved spare; bank voltage and special functions still matter." }, { "pin": "B10", "function": "VCCO_16", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "B11", "function": "IO_L4P_T0_15", "net": "IMP_TST_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified. IMP_TST is provisionally treated as a 0/1.5 V digital output; inactive polarity and timing remain unverified." }, { "pin": "B12", "function": "IO_L3N_T0_DQS_AD1N_15", "net": "STIM_CHB_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B13", "function": "IO_L2P_T0_AD8P_15", "net": "BOARD2_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B14", "function": "IO_L2N_T0_AD8N_15", "net": "FE_RESET_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B15", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "B16", "function": "IO_L7P_T1_AD2P_15", "net": "BOARD1_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B17", "function": "IO_L7N_T1_AD2N_15", "net": "BOARD1_SPI_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "B18", "function": "IO_L10P_T1_AD11P_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "C1", "function": "IO_L16N_T2_35", "net": "ASIC1_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C2", "function": "IO_L16P_T2_35", "net": "ASIC2_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C3", "function": "VCCO_35", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "C4", "function": "IO_L7P_T1_AD6P_35", "net": "ASIC2_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C5", "function": "IO_L1N_T0_AD4N_35", "net": "ASIC4_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C6", "function": "IO_L1P_T0_AD4P_35", "net": "ASIC4_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C7", "function": "IO_L4N_T0_35", "net": "ASIC4_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C8", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "C9", "function": "IO_L11P_T1_SRCC_16", "net": "", "status": "reserved — interface implementation required", "note": "No functional net is assigned. The 116 candidate digital ASIC signals have other package balls. This ball is not automatically an approved spare; bank voltage and special functions still matter." }, { "pin": "C10", "function": "IO_L13N_T2_MRCC_16", "net": "", "status": "reserved — interface implementation required", "note": "No functional net is assigned. The 116 candidate digital ASIC signals have other package balls. This ball is not automatically an approved spare; bank voltage and special functions still matter." }, { "pin": "C11", "function": "IO_L13P_T2_MRCC_16", "net": "", "status": "reserved — interface implementation required", "note": "No functional net is assigned. The 116 candidate digital ASIC signals have other package balls. This ball is not automatically an approved spare; bank voltage and special functions still matter." }, { "pin": "C12", "function": "IO_L3P_T0_DQS_AD1P_15", "net": "STIM_START_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C13", "function": "VCCO_15", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "C14", "function": "IO_L1N_T0_AD0N_15", "net": "BOARD4_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C15", "function": "IO_L12N_T1_MRCC_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "C16", "function": "IO_L20P_T3_A20_15", "net": "STIM_CLK_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "C17", "function": "IO_L20N_T3_A19_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "C18", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "D1", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "D2", "function": "IO_L14N_T2_SRCC_35", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball E2; no differential receiver instantiated. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D3", "function": "IO_L12N_T1_MRCC_35", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball E3; no differential receiver instantiated. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D4", "function": "IO_L11N_T1_SRCC_35", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball D5; no differential receiver instantiated. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D5", "function": "IO_L11P_T1_SRCC_35", "net": "ASIC4_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "D6", "function": "VCCO_35", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "D7", "function": "IO_L6N_T0_VREF_35", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D8", "function": "IO_L4P_T0_35", "net": "ASIC4_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "D9", "function": "IO_L6N_T0_VREF_16", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D10", "function": "IO_L19N_T3_VREF_16", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D11", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "D12", "function": "IO_L6P_T0_15", "net": "CHIP_RESET_SHARED", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "D13", "function": "IO_L6N_T0_VREF_15", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D14", "function": "IO_L1P_T0_AD0P_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D15", "function": "IO_L12P_T1_MRCC_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D16", "function": "VCCO_15", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "D17", "function": "IO_L16N_T2_A27_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "D18", "function": "IO_L21N_T3_DQS_A18_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "E1", "function": "IO_L18N_T2_35", "net": "ASIC1_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "E2", "function": "IO_L14P_T2_SRCC_35", "net": "ASIC1_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "E3", "function": "IO_L12P_T1_MRCC_35", "net": "ASIC2_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "E4", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "E5", "function": "IO_L5N_T0_AD13N_35", "net": "ASIC3_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "E6", "function": "IO_L5P_T0_AD13P_35", "net": "ASIC3_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "E7", "function": "IO_L6P_T0_35", "net": "ASIC4_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "E8", "function": "VCCBATT_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "E9", "function": "CCLK_0", "net": "FPGA_CCLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "E10", "function": "TCK_0", "net": "JTAG_TCK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "E11", "function": "TDI_0", "net": "JTAG_TDI", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "E12", "function": "TMS_0", "net": "JTAG_TMS", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "E13", "function": "TDO_0", "net": "FPGA_TDO", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "E14", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "E15", "function": "IO_L11P_T1_SRCC_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "E16", "function": "IO_L11N_T1_SRCC_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "E17", "function": "IO_L16P_T2_A28_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "E18", "function": "IO_L21P_T3_DQS_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "F1", "function": "IO_L18P_T2_35", "net": "ASIC1_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "F2", "function": "VCCO_35", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "F3", "function": "IO_L13N_T2_MRCC_35", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball F4; no differential receiver instantiated. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "F4", "function": "IO_L13P_T2_MRCC_35", "net": "ASIC3_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "F5", "function": "IO_0_35", "net": "ASIC3_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "F6", "function": "IO_L19N_T3_VREF_35", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "F7", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "F8", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "F9", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "F10", "function": "VCCBRAM", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "F11", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "F12", "function": "VCCAUX", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "F13", "function": "IO_L5P_T0_AD9P_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "F14", "function": "IO_L5N_T0_AD9N_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "F15", "function": "IO_L14P_T2_SRCC_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "F16", "function": "IO_L14N_T2_SRCC_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "F17", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "F18", "function": "IO_L22N_T3_A16_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "G1", "function": "IO_L17N_T2_35", "net": "ASIC1_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G2", "function": "IO_L15N_T2_DQS_35", "net": "ASIC1_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G3", "function": "IO_L20N_T3_35", "net": "ASIC2_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G4", "function": "IO_L20P_T3_35", "net": "ASIC3_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G5", "function": "VCCO_35", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "G6", "function": "IO_L19P_T3_35", "net": "ASIC3_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G7", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "G8", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "G9", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "G10", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "G11", "function": "VCCBRAM", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "G12", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "G13", "function": "IO_0_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "G14", "function": "IO_L15N_T2_DQS_ADV_B_15", "net": "STIM_CHIP2_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G15", "function": "VCCO_15", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "G16", "function": "IO_L13N_T2_MRCC_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "G17", "function": "IO_L18N_T2_A23_15", "net": "NONSTIM_BOARD1_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "G18", "function": "IO_L22P_T3_A17_15", "net": "NONSTIM_BOARD2_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "H1", "function": "IO_L17P_T2_35", "net": "ASIC1_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "H2", "function": "IO_L15P_T2_DQS_35", "net": "ASIC2_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "H3", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "H4", "function": "IO_L21N_T3_DQS_35", "net": "ASIC3_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "H5", "function": "IO_L24N_T3_35", "net": "ASIC3_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "H6", "function": "IO_L24P_T3_35", "net": "ASIC3_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "H7", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "H8", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "H9", "function": "GNDADC_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "H10", "function": "VCCADC_0", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "H11", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "H12", "function": "VCCAUX", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "H13", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "H14", "function": "IO_L15P_T2_DQS_15", "net": "STIM_CHIP2_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "H15", "function": "IO_L19N_T3_A21_VREF_15", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "H16", "function": "IO_L13P_T2_MRCC_15", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "H17", "function": "IO_L18P_T2_A24_15", "net": "NONSTIM_BOARD1_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "H18", "function": "VCCO_15", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J1", "function": "VCCO_35", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J2", "function": "IO_L22N_T3_35", "net": "ASIC1_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "J3", "function": "IO_L22P_T3_35", "net": "ASIC2_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "J4", "function": "IO_L21P_T3_DQS_35", "net": "ASIC3_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "J5", "function": "IO_25_35", "net": "ASIC3_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "J6", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J7", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J8", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J9", "function": "VREFN_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J10", "function": "VP_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J11", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J12", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J13", "function": "IO_L17N_T2_A25_15", "net": "STIM_CHIP1_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "J14", "function": "IO_L19P_T3_A22_15", "net": "STIM_CHIP1_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "J15", "function": "IO_L24N_T3_RS0_15", "net": "STIM_CHIP3_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "J16", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "J17", "function": "IO_L23P_T3_FOE_B_15", "net": "STIM_CHIP4_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "J18", "function": "IO_L23N_T3_FWE_B_15", "net": "NONSTIM_BOARD2_SPI_DL", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K1", "function": "IO_L23N_T3_35", "net": "ASIC1_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K2", "function": "IO_L23P_T3_35", "net": "ASIC1_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K3", "function": "IO_L2P_T0_34", "net": "ASIC6_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K4", "function": "VCCO_34", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K5", "function": "IO_L5P_T0_34", "net": "ASIC8_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K6", "function": "IO_0_34", "net": "ASIC8_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K7", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K8", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K9", "function": "VN_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K10", "function": "VREFP_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K11", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K12", "function": "VCCAUX", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K13", "function": "IO_L17P_T2_A26_15", "net": "BOARD4_SPI_CLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K14", "function": "VCCO_15", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K15", "function": "IO_L24P_T3_RS1_15", "net": "STIM_CHIP3_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K16", "function": "IO_25_15", "net": "STIM_CHIP4_SPI_DR", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "K17", "function": "IO_L1P_T0_D00_MOSI_14", "net": "FPGA_CFG_DQ0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "K18", "function": "IO_L1N_T0_D01_DIN_14", "net": "FPGA_CFG_DQ1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L1", "function": "IO_L1P_T0_34", "net": "ASIC6_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "L2", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L3", "function": "IO_L2N_T0_34", "net": "ASIC6_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "L4", "function": "IO_L5N_T0_34", "net": "ASIC8_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "L5", "function": "IO_L6N_T0_VREF_34", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "L6", "function": "IO_L6P_T0_34", "net": "ASIC8_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "L7", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L8", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L9", "function": "DXN_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. The earlier NC marker was removed and the native pin is now GND. Assignment and physical copper completion are different checks." }, { "pin": "L10", "function": "DXP_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. The earlier NC marker was removed and the native pin is now GND. Assignment and physical copper completion are different checks." }, { "pin": "L11", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L12", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L13", "function": "IO_L6P_T0_FCS_B_14", "net": "FLASH_CS_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L14", "function": "IO_L2P_T0_D02_14", "net": "", "status": "intentional no-connect", "note": "Unused optional quad-SPI configuration data pin. The selected Master SPI x1 boot uses CS, CCLK, DQ0 and DQ1. R106/R107 are removed; flash WP# and RESET# retain their separate pull-ups. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "L15", "function": "IO_L3P_T0_DQS_PUDC_B_14", "net": "CFG_PUDC_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L16", "function": "IO_L3N_T0_DQS_EMCCLK_14", "net": "", "status": "intentional no-connect", "note": "EMCCLK is unused; master SPI uses internal CCLK. Keep EXTMASTERCCLK_EN disabled. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "L17", "function": "VCCO_14", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "L18", "function": "IO_L4P_T0_D04_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "M1", "function": "IO_L1N_T0_34", "net": "ASIC6_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "M2", "function": "IO_L4N_T0_34", "net": "ASIC6_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "M3", "function": "IO_L4P_T0_34", "net": "ASIC6_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "M4", "function": "IO_L16P_T2_34", "net": "ASIC8_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "M5", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "M6", "function": "IO_L18P_T2_34", "net": "ASIC8_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "M7", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "M8", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "M9", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "M10", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "M11", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "M12", "function": "VCCAUX", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "M13", "function": "IO_L6N_T0_D08_VREF_14", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "M14", "function": "IO_L2N_T0_D03_14", "net": "", "status": "intentional no-connect", "note": "Unused optional quad-SPI configuration data pin. The selected Master SPI x1 boot uses CS, CCLK, DQ0 and DQ1. R106/R107 are removed; flash WP# and RESET# retain their separate pull-ups. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "M15", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "M16", "function": "IO_L10P_T1_D14_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "M17", "function": "IO_L10N_T1_D15_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "M18", "function": "IO_L4N_T0_D05_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "N1", "function": "IO_L3N_T0_DQS_34", "net": "ASIC6_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "N2", "function": "IO_L3P_T0_DQS_34", "net": "ASIC6_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "N3", "function": "VCCO_34", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "N4", "function": "IO_L16N_T2_34", "net": "ASIC6_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "N5", "function": "IO_L13P_T2_MRCC_34", "net": "ASIC8_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "N6", "function": "IO_L18N_T2_34", "net": "ASIC8_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "N7", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "N8", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "N9", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "N10", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "N11", "function": "VCCINT", "net": "VCCINT_1V0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "N12", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "N13", "function": "VCCO_14", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "N14", "function": "IO_L8P_T1_D11_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "N15", "function": "IO_L11P_T1_SRCC_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "N16", "function": "IO_L11N_T1_SRCC_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "N17", "function": "IO_L9P_T1_DQS_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "N18", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P1", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P2", "function": "IO_L15P_T2_DQS_34", "net": "ASIC5_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "P3", "function": "IO_L14N_T2_SRCC_34", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball P4; no differential receiver instantiated. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "P4", "function": "IO_L14P_T2_SRCC_34", "net": "ASIC6_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "P5", "function": "IO_L13N_T2_MRCC_34", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball N5; no differential receiver instantiated. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "P6", "function": "VCCO_34", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P7", "function": "INIT_B_0", "net": "FPGA_INIT_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P8", "function": "CFGBVS_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P9", "function": "PROGRAM_B_0", "net": "FPGA_PROGRAM_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P10", "function": "DONE_0", "net": "FPGA_DONE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P11", "function": "M2_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. M2 is tied directly to GND and R113 is omitted, as permitted by UG470. Master SPI mode 001 and normal JTAG access remain; changing to mode 101 for isolated debug now requires a copper rework instead of a resistor change." }, { "pin": "P12", "function": "M0_0", "net": "CFG_M0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P13", "function": "M1_0", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. This revision replaces the M1 pull-down resistor R112 with a direct GND connection; SPI mode selection is preserved by the defined M[2:0] straps." }, { "pin": "P14", "function": "IO_L8N_T1_D12_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "P15", "function": "IO_L13P_T2_MRCC_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "P16", "function": "VCCO_14", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P17", "function": "IO_L12P_T1_MRCC_14", "net": "CLK_32MHZ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "P18", "function": "IO_L9N_T1_DQS_D13_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R1", "function": "IO_L17P_T2_34", "net": "ASIC5_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "R2", "function": "IO_L15N_T2_DQS_34", "net": "ASIC5_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "R3", "function": "IO_L11P_T1_SRCC_34", "net": "ASIC5_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "R4", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "R5", "function": "IO_L19N_T3_VREF_34", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R6", "function": "IO_L19P_T3_34", "net": "ASIC6_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "R7", "function": "IO_L23P_T3_34", "net": "ASIC8_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "R8", "function": "IO_L24P_T3_34", "net": "ASIC8_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "R9", "function": "VCCO_0", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "R10", "function": "IO_25_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R11", "function": "IO_0_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R12", "function": "IO_L5P_T0_D06_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R13", "function": "IO_L5N_T0_D07_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R14", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "R15", "function": "IO_L13N_T2_MRCC_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R16", "function": "IO_L15P_T2_DQS_RDWR_B_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R17", "function": "IO_L12N_T1_MRCC_14", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended oscillator P17. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "R18", "function": "IO_L7P_T1_D09_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T1", "function": "IO_L17N_T2_34", "net": "ASIC5_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "T2", "function": "VCCO_34", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "T3", "function": "IO_L11N_T1_SRCC_34", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball R3; no differential receiver instantiated. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T4", "function": "IO_L12N_T1_MRCC_34", "net": "", "status": "intentional no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball T5; no differential receiver instantiated. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T5", "function": "IO_L12P_T1_MRCC_34", "net": "ASIC7_CLK32MHz_Out", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "T6", "function": "IO_L23N_T3_34", "net": "ASIC7_SYNC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "T7", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "T8", "function": "IO_L24N_T3_34", "net": "ASIC8_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "T9", "function": "IO_L24P_T3_A01_D17_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T10", "function": "IO_L24N_T3_A00_D16_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T11", "function": "IO_L19P_T3_A10_D26_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T12", "function": "VCCO_14", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "T13", "function": "IO_L23P_T3_A03_D19_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T14", "function": "IO_L14P_T2_SRCC_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T15", "function": "IO_L14N_T2_SRCC_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T16", "function": "IO_L15N_T2_DQS_DOUT_CSO_B_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "T17", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "T18", "function": "IO_L7N_T1_D10_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "U1", "function": "IO_L7P_T1_34", "net": "ASIC5_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "U2", "function": "IO_L9P_T1_DQS_34", "net": "ASIC5_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "U3", "function": "IO_L8N_T1_34", "net": "ASIC5_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "U4", "function": "IO_L8P_T1_34", "net": "ASIC7_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "U5", "function": "VCCO_34", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "U6", "function": "IO_L22N_T3_34", "net": "ASIC7_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "U7", "function": "IO_L22P_T3_34", "net": "ASIC7_DATA4", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "U8", "function": "IO_25_34", "net": "ASIC7_DATA6", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "U9", "function": "IO_L21P_T3_DQS_34", "net": "ASIC7_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "U10", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "U11", "function": "IO_L19N_T3_A09_D25_VREF_14", "net": "", "status": "intentional no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "U12", "function": "IO_L20P_T3_A08_D24_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "U13", "function": "IO_L23N_T3_A02_D18_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "U14", "function": "IO_L22P_T3_A05_D21_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "U15", "function": "VCCO_14", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "U16", "function": "IO_L18P_T2_A12_D28_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "U17", "function": "IO_L17P_T2_A14_D30_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "U18", "function": "IO_L17N_T2_A13_D29_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "V1", "function": "IO_L7N_T1_34", "net": "ASIC5_DATA1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "V2", "function": "IO_L9N_T1_DQS_34", "net": "ASIC5_DATA7", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "V3", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "V4", "function": "IO_L10N_T1_34", "net": "ASIC5_READ", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "V5", "function": "IO_L10P_T1_34", "net": "ASIC7_DATA3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "V6", "function": "IO_L20N_T3_34", "net": "ASIC7_DATA5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "V7", "function": "IO_L20P_T3_34", "net": "ASIC7_DATA2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "V8", "function": "VCCO_34", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "V9", "function": "IO_L21N_T3_DQS_34", "net": "ASIC7_DATA8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. Provisional ASIC assignment: electrical limits, physical chip identity, mating continuity and capture timing remain unverified." }, { "pin": "V10", "function": "IO_L21P_T3_DQS_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "V11", "function": "IO_L21N_T3_DQS_A06_D22_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "V12", "function": "IO_L20N_T3_A07_D23_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "V13", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "V14", "function": "IO_L22N_T3_A04_D20_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "V15", "function": "IO_L16P_T2_CSI_B_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "V16", "function": "IO_L16N_T2_A15_D31_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "V17", "function": "IO_L18N_T2_A11_D27_14", "net": "", "status": "intentional no-connect", "note": "No function or physical net in this revision; no boot/power pin removed. The schematic NC marker documents intent; the bitstream must also set its unused-pin behavior." }, { "pin": "V18", "function": "VCCO_14", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "FPGA100T:Xilinx_CSG324" }, { "reference": "U2", "value": "TPS62135RGXR", "mpn": "TPS62135RGXR", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_core", "side": "Back", "status": "required", "shortRole": "Core / block ram converter", "whyNeeded": "Converts the proposed 12 V input into the core / block RAM rail. Its output voltage is selected by R1/R2.", "ifRemoved": "This rail loses its source. The connected FPGA power pins cannot simply be left open.", "reviewDecision": "Keep for this four-rail architecture. A different input or interface voltage requires redesign; the 4 A IC rating is not a validated available board current.", "sourceIds": [ "TI", "DS181", "LOCAL" ], "pins": [ { "pin": "1", "function": "VIN", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "SW", "net": "SW_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "3", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "4", "function": "FB2", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. The earlier NC marker was removed and the native pin is now GND. Assignment and physical copper completion are different checks." }, { "pin": "5", "function": "FB", "net": "FB_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "6", "function": "VOS", "net": "VCORE_REG_1V025", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "7", "function": "PG", "net": "PG_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "8", "function": "EN", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "9", "function": "SS/TR", "net": "SS_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "10", "function": "MODE", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "11", "function": "VSEL", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:PowerDraft__Texas_VQFN_RGX0011A_2x3mm" }, { "reference": "U3", "value": "TPS62135RGXR", "mpn": "TPS62135RGXR", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_aux", "side": "Front", "status": "required", "shortRole": "Auxiliary / configuration converter", "whyNeeded": "Converts the proposed 12 V input into the auxiliary / configuration rail. Its output voltage is selected by R3/R4.", "ifRemoved": "This rail loses its source. The connected FPGA power pins cannot simply be left open.", "reviewDecision": "Keep for this four-rail architecture. A different input or interface voltage requires redesign; the 4 A IC rating is not a validated available board current.", "sourceIds": [ "TI", "DS181", "LOCAL" ], "pins": [ { "pin": "1", "function": "VIN", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "SW", "net": "SW_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "3", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "4", "function": "FB2", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. The earlier NC marker was removed and the native pin is now GND. Assignment and physical copper completion are different checks." }, { "pin": "5", "function": "FB", "net": "FB_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "6", "function": "VOS", "net": "VAUX_REG_1V803", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "7", "function": "PG", "net": "PG_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "8", "function": "EN", "net": "PG_CORE", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "9", "function": "SS/TR", "net": "SS_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "10", "function": "MODE", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "11", "function": "VSEL", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:PowerDraft__Texas_VQFN_RGX0011A_2x3mm" }, { "reference": "U4", "value": "TPS62135RGXR", "mpn": "TPS62135RGXR", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_cfg", "side": "Front", "status": "architecture", "shortRole": "2.5 v link bank converter", "whyNeeded": "Converts the proposed 12 V input into the 2.5 V link bank rail. Its output voltage is selected by R5/R6.", "ifRemoved": "This rail loses its source. The connected FPGA power pins cannot simply be left open.", "reviewDecision": "Keep for this four-rail architecture. A different input or interface voltage requires redesign; the 4 A IC rating is not a validated available board current.", "sourceIds": [ "TI", "DS181", "LOCAL" ], "pins": [ { "pin": "1", "function": "VIN", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "SW", "net": "SW_CFG", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "3", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "4", "function": "FB2", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. The earlier NC marker was removed and the native pin is now GND. Assignment and physical copper completion are different checks." }, { "pin": "5", "function": "FB", "net": "FB_CFG", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "6", "function": "VOS", "net": "VCC_LINK_2V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "7", "function": "PG", "net": "", "status": "intentional no-connect", "note": "Unused open-drain power-good output. Its shared status branch and R12 were removed because no circuit consumed the signal. TI permits unused PG to be left open." }, { "pin": "8", "function": "EN", "net": "PG_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "9", "function": "SS/TR", "net": "SS_CFG", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "10", "function": "MODE", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "11", "function": "VSEL", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:PowerDraft__Texas_VQFN_RGX0011A_2x3mm" }, { "reference": "U5", "value": "TPS62135RGXR", "mpn": "TPS62135RGXR", "group": "power", "groupLabel": "Four power rails", "originalGroup": "power_asic", "side": "Back", "status": "architecture", "shortRole": "1.5 v asic-facing banks converter", "whyNeeded": "Converts the proposed 12 V input into the 1.5 V ASIC-facing banks rail. Its output voltage is selected by R7/R8.", "ifRemoved": "This rail loses its source. The connected FPGA power pins cannot simply be left open.", "reviewDecision": "Keep for this four-rail architecture. A different input or interface voltage requires redesign; the 4 A IC rating is not a validated available board current.", "sourceIds": [ "TI", "DS181", "LOCAL" ], "pins": [ { "pin": "1", "function": "VIN", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "SW", "net": "SW_ASIC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "3", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "4", "function": "FB2", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test. The earlier NC marker was removed and the native pin is now GND. Assignment and physical copper completion are different checks." }, { "pin": "5", "function": "FB", "net": "FB_ASIC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "6", "function": "VOS", "net": "VCC_ASIC_1V5", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "7", "function": "PG", "net": "", "status": "intentional no-connect", "note": "Unused open-drain power-good output. Its shared status branch and R12 were removed because no circuit consumed the signal. TI permits unused PG to be left open." }, { "pin": "8", "function": "EN", "net": "PG_AUX", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "9", "function": "SS/TR", "net": "SS_ASIC", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "10", "function": "MODE", "net": "LINK_12V", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "11", "function": "VSEL", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:PowerDraft__Texas_VQFN_RGX0011A_2x3mm" }, { "reference": "U6", "value": "MX25U12835FM2I-10G", "mpn": "MX25U12835FM2I-10G", "group": "boot", "groupLabel": "Boot memory", "originalGroup": "Boot flash", "side": "Back", "status": "architecture", "shortRole": "Nonvolatile boot image", "whyNeeded": "Stores the configuration image for autonomous SPI boot at 1.8 V. The FPGA logic configuration must be loaded after power-up.", "ifRemoved": "The selected SPI self-boot path is lost; an external configuration method would be required each startup.", "reviewDecision": "Keep for autonomous Master SPI x1 boot at 1.8 V. R106/R107 and FPGA DQ2/DQ3 paths are omitted. Use a compatible SPI x1 image and validated flash-programming procedure; quad configuration is not supported by this wiring.", "sourceIds": [ "UG470", "MX", "LOCAL" ], "pins": [ { "pin": "1", "function": "CS#", "net": "FLASH_CS_B", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "SO / SIO1", "net": "FLASH_DQ1", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "3", "function": "WP# / SIO2", "net": "FLASH_DQ2", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "4", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "5", "function": "SI / SIO0", "net": "FLASH_DQ0", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "6", "function": "SCLK", "net": "FLASH_SCLK", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "7", "function": "RESET# / SIO3", "net": "FLASH_DQ3", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "8", "function": "VCC", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Package_SO__SOIC-8_5_3x5_3mm_P1_27mm" }, { "reference": "Y1", "value": "ASE3 32MHz 1.8V", "mpn": "ASE3-32.000MHZ-L-C-T", "group": "clock", "groupLabel": "System clock", "originalGroup": "Reference clock", "side": "Front", "status": "architecture", "shortRole": "32 MHz system reference", "whyNeeded": "The 1.8 V oscillator provides the application clock through R119 to U1.P17. It is separate from the FPGA configuration clock.", "ifRemoved": "The present application clock path stops; SPI configuration may still use its own clock, but application operation requires an alternative reference.", "reviewDecision": "Keep for self-contained clocking. Remove only if another approved clock source is supplied with valid startup and timing.", "sourceIds": [ "ASE", "LOCAL" ], "pins": [ { "pin": "1", "function": "Enable", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "2", "function": "GND", "net": "GND", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "3", "function": "Clock output", "net": "OSC_32M_RAW", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." }, { "pin": "4", "function": "VDD", "net": "VCCAUX_1V8", "status": "assigned net connected in native DRC", "note": "This assigned net has no missing connection in the supplied native DRC. This is copper connectivity, not electrical compatibility or a powered test." } ], "footprint": "CoreSupport:Oscillator__Oscillator_SMD_Abracon_ASE-4Pin_3_2x2_5mm" } ], "intentionalNoConnects": [ { "reference": "U1", "pin": "A13", "net": "unconnected-(U1A-IO_L9P_T1_DQS_AD3P_15-PadA13)", "reviewState": "intentional-no-connect", "note": "AC_IN analog is provided on carrier; no FPGA connection permitted under current design." }, { "reference": "U1", "pin": "B18", "net": "unconnected-(U1A-IO_L10P_T1_AD11P_15-PadB18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "C15", "net": "unconnected-(U1A-IO_L12N_T1_MRCC_15-PadC15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "C17", "net": "unconnected-(U1A-IO_L20N_T3_A19_15-PadC17)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "D10", "net": "unconnected-(U1B-IO_L19N_T3_VREF_16-PadD10)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "D13", "net": "unconnected-(U1A-IO_L6N_T0_VREF_15-PadD13)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "D14", "net": "unconnected-(U1A-IO_L1P_T0_AD0P_15-PadD14)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "D15", "net": "unconnected-(U1A-IO_L12P_T1_MRCC_15-PadD15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "D17", "net": "unconnected-(U1A-IO_L16N_T2_A27_15-PadD17)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "D18", "net": "unconnected-(U1A-IO_L21N_T3_DQS_A18_15-PadD18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "D2", "net": "unconnected-(U1C-IO_L14N_T2_SRCC_35-PadD2)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball E2; no differential receiver instantiated." }, { "reference": "U1", "pin": "D3", "net": "unconnected-(U1C-IO_L12N_T1_MRCC_35-PadD3)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball E3; no differential receiver instantiated." }, { "reference": "U1", "pin": "D4", "net": "unconnected-(U1C-IO_L11N_T1_SRCC_35-PadD4)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball D5; no differential receiver instantiated." }, { "reference": "U1", "pin": "D7", "net": "unconnected-(U1C-IO_L6N_T0_VREF_35-PadD7)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "D9", "net": "unconnected-(U1B-IO_L6N_T0_VREF_16-PadD9)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "E15", "net": "unconnected-(U1A-IO_L11P_T1_SRCC_15-PadE15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "E16", "net": "unconnected-(U1A-IO_L11N_T1_SRCC_15-PadE16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "E17", "net": "unconnected-(U1A-IO_L16P_T2_A28_15-PadE17)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "E18", "net": "unconnected-(U1A-IO_L21P_T3_DQS_15-PadE18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "F13", "net": "unconnected-(U1A-IO_L5P_T0_AD9P_15-PadF13)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "F14", "net": "unconnected-(U1A-IO_L5N_T0_AD9N_15-PadF14)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "F15", "net": "unconnected-(U1A-IO_L14P_T2_SRCC_15-PadF15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "F16", "net": "unconnected-(U1A-IO_L14N_T2_SRCC_15-PadF16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "F18", "net": "unconnected-(U1A-IO_L22N_T3_A16_15-PadF18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "F3", "net": "unconnected-(U1C-IO_L13N_T2_MRCC_35-PadF3)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball F4; no differential receiver instantiated." }, { "reference": "U1", "pin": "F6", "net": "unconnected-(U1C-IO_L19N_T3_VREF_35-PadF6)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "G13", "net": "unconnected-(U1A-IO_0_15-PadG13)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "G16", "net": "unconnected-(U1A-IO_L13N_T2_MRCC_15-PadG16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "H15", "net": "unconnected-(U1A-IO_L19N_T3_A21_VREF_15-PadH15)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "H16", "net": "unconnected-(U1A-IO_L13P_T2_MRCC_15-PadH16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "L14", "net": "unconnected-(U1A-IO_L2P_T0_D02_14-PadL14)", "reviewState": "intentional-no-connect", "note": "Unused optional quad-SPI configuration data pin. The selected Master SPI x1 boot uses CS, CCLK, DQ0 and DQ1. R106/R107 are removed; flash WP# and RESET# retain their separate pull-ups." }, { "reference": "U1", "pin": "L16", "net": "unconnected-(U1A-IO_L3N_T0_DQS_EMCCLK_14-PadL16)", "reviewState": "intentional-no-connect", "note": "EMCCLK is unused; master SPI uses internal CCLK. Keep EXTMASTERCCLK_EN disabled." }, { "reference": "U1", "pin": "L18", "net": "unconnected-(U1A-IO_L4P_T0_D04_14-PadL18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "L5", "net": "unconnected-(U1B-IO_L6N_T0_VREF_34-PadL5)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "M13", "net": "unconnected-(U1A-IO_L6N_T0_D08_VREF_14-PadM13)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "M14", "net": "unconnected-(U1A-IO_L2N_T0_D03_14-PadM14)", "reviewState": "intentional-no-connect", "note": "Unused optional quad-SPI configuration data pin. The selected Master SPI x1 boot uses CS, CCLK, DQ0 and DQ1. R106/R107 are removed; flash WP# and RESET# retain their separate pull-ups." }, { "reference": "U1", "pin": "M16", "net": "unconnected-(U1A-IO_L10P_T1_D14_14-PadM16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "M17", "net": "unconnected-(U1A-IO_L10N_T1_D15_14-PadM17)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "M18", "net": "unconnected-(U1A-IO_L4N_T0_D05_14-PadM18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "N14", "net": "unconnected-(U1A-IO_L8P_T1_D11_14-PadN14)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "N15", "net": "unconnected-(U1A-IO_L11P_T1_SRCC_14-PadN15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "N16", "net": "unconnected-(U1A-IO_L11N_T1_SRCC_14-PadN16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "N17", "net": "unconnected-(U1A-IO_L9P_T1_DQS_14-PadN17)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "P14", "net": "unconnected-(U1A-IO_L8N_T1_D12_14-PadP14)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "P15", "net": "unconnected-(U1A-IO_L13P_T2_MRCC_14-PadP15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "P18", "net": "unconnected-(U1A-IO_L9N_T1_DQS_D13_14-PadP18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "P3", "net": "unconnected-(U1B-IO_L14N_T2_SRCC_34-PadP3)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball P4; no differential receiver instantiated." }, { "reference": "U1", "pin": "P5", "net": "unconnected-(U1B-IO_L13N_T2_MRCC_34-PadP5)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball N5; no differential receiver instantiated." }, { "reference": "U1", "pin": "R10", "net": "unconnected-(U1A-IO_25_14-PadR10)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "R11", "net": "unconnected-(U1A-IO_0_14-PadR11)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "R12", "net": "unconnected-(U1A-IO_L5P_T0_D06_14-PadR12)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "R13", "net": "unconnected-(U1A-IO_L5N_T0_D07_14-PadR13)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "R15", "net": "unconnected-(U1A-IO_L13N_T2_MRCC_14-PadR15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "R16", "net": "unconnected-(U1A-IO_L15P_T2_DQS_RDWR_B_14-PadR16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "R17", "net": "unconnected-(U1A-IO_L12N_T1_MRCC_14-PadR17)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended oscillator P17." }, { "reference": "U1", "pin": "R18", "net": "unconnected-(U1A-IO_L7P_T1_D09_14-PadR18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "R5", "net": "unconnected-(U1B-IO_L19N_T3_VREF_34-PadR5)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "T10", "net": "unconnected-(U1A-IO_L24N_T3_A00_D16_14-PadT10)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "T11", "net": "unconnected-(U1A-IO_L19P_T3_A10_D26_14-PadT11)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "T13", "net": "unconnected-(U1A-IO_L23P_T3_A03_D19_14-PadT13)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "T14", "net": "unconnected-(U1A-IO_L14P_T2_SRCC_14-PadT14)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "T15", "net": "unconnected-(U1A-IO_L14N_T2_SRCC_14-PadT15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "T16", "net": "unconnected-(U1A-IO_L15N_T2_DQS_DOUT_CSO_B_14-PadT16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "T18", "net": "unconnected-(U1A-IO_L7N_T1_D10_14-PadT18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "T3", "net": "unconnected-(U1B-IO_L11N_T1_SRCC_34-PadT3)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball R3; no differential receiver instantiated." }, { "reference": "U1", "pin": "T4", "net": "unconnected-(U1B-IO_L12N_T1_MRCC_34-PadT4)", "reviewState": "intentional-no-connect", "note": "Unused N mate of single-ended LVCMOS15 returned-clock P ball T5; no differential receiver instantiated." }, { "reference": "U1", "pin": "T9", "net": "unconnected-(U1A-IO_L24P_T3_A01_D17_14-PadT9)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "U11", "net": "unconnected-(U1A-IO_L19N_T3_A09_D25_VREF_14-PadU11)", "reviewState": "intentional-no-connect", "note": "GPIO/multifunction VREF alias; selected LVCMOS15/LVDS_25/1.8V configuration interface needs no external VREF here." }, { "reference": "U1", "pin": "U12", "net": "unconnected-(U1A-IO_L20P_T3_A08_D24_14-PadU12)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "U13", "net": "unconnected-(U1A-IO_L23N_T3_A02_D18_14-PadU13)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "U14", "net": "unconnected-(U1A-IO_L22P_T3_A05_D21_14-PadU14)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "U16", "net": "unconnected-(U1A-IO_L18P_T2_A12_D28_14-PadU16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "U17", "net": "unconnected-(U1A-IO_L17P_T2_A14_D30_14-PadU17)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "U18", "net": "unconnected-(U1A-IO_L17N_T2_A13_D29_14-PadU18)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "V10", "net": "unconnected-(U1A-IO_L21P_T3_DQS_14-PadV10)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "V11", "net": "unconnected-(U1A-IO_L21N_T3_DQS_A06_D22_14-PadV11)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "V12", "net": "unconnected-(U1A-IO_L20N_T3_A07_D23_14-PadV12)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "V14", "net": "unconnected-(U1A-IO_L22N_T3_A04_D20_14-PadV14)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "V15", "net": "unconnected-(U1A-IO_L16P_T2_CSI_B_14-PadV15)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "V16", "net": "unconnected-(U1A-IO_L16N_T2_A15_D31_14-PadV16)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U1", "pin": "V17", "net": "unconnected-(U1A-IO_L18N_T2_A11_D27_14-PadV17)", "reviewState": "intentional-no-connect", "note": "No function or physical net in this revision; no boot/power pin removed." }, { "reference": "U4", "pin": "7", "net": "unconnected-(U4-PG-Pad7)", "reviewState": "intentional-no-connect", "note": "Unused open-drain power-good output. Its shared status branch and R12 were removed because no circuit consumed the signal. TI permits unused PG to be left open." }, { "reference": "U5", "pin": "7", "net": "unconnected-(U5-PG-Pad7)", "reviewState": "intentional-no-connect", "note": "Unused open-drain power-good output. Its shared status branch and R12 were removed because no circuit consumed the signal. TI permits unused PG to be left open." } ], "counts": { "components": 125, "pins": 752, "byStatus": { "qualification": 82, "required": 32, "architecture": 11 }, "byPrefix": { "C": 83, "J": 3, "L": 4, "R": 28, "U": 6, "Y": 1 } }, "pinStatusCaution": "102 endpoints without a functional net comprise 83 intentional NCs (81 FPGA balls, two regulator outputs) and 19 future-interface reservations. There are 116 candidate digital FPGA nets plus one external analog contact. Missing copper, ASIC limits, mating and timing remain separate checks.", "fabricationReady": false, "cadModified": false, "newFindings": [ { "id": "DX_DIODE_GROUND", "severity": "assignment-corrected", "endpoints": [ "U1.L9", "U1.L10" ], "summary": "Both temperature-diode pins now have native GND assignments; see the current routing audit for physical continuity.", "sourceIds": [ "UG475" ] }, { "id": "FB2_UNUSED", "severity": "assignment-corrected", "endpoints": [ "U2.4", "U3.4", "U4.4", "U5.4" ], "summary": "Unused switched-divider FB2 pins now have native GND assignments. Physical continuity and ERC symbol modeling are separate checks.", "sourceIds": [ "TI" ] }, { "id": "AC_IN_ANALOG", "severity": "electrical-review", "endpoints": [ "J5.46", "U1.A13" ], "summary": "AC_IN is analog 0–1.5 V. J5.46 is reserved for an external analog source; the direct FPGA path is removed and U1.A13 is NC. Source circuitry and loading remain open.", "sourceIds": [ "LOCAL" ] }, { "id": "IMP_TST_PROVISIONAL", "severity": "electrical-review", "endpoints": [ "U1.B11", "J5.47" ], "summary": "IMP_TST is provisionally digital 0/1.5 V; inactive polarity and timing remain unverified.", "sourceIds": [ "LOCAL" ] }, { "id": "M1_DIRECT_GROUND", "severity": "assignment-corrected", "endpoints": [ "U1.P13" ], "summary": "R112 is absent from this supplied native revision; M1 at U1.P13 is tied directly to GND. The configuration mode remains SPI when the other straps retain their values.", "sourceIds": [ "UG470" ] }, { "id": "M2_DIRECT_GROUND", "severity": "assignment-corrected", "endpoints": [ "U1.P11" ], "summary": "R113 is omitted; M2 is tied directly to GND, preserving fixed Master SPI 001 and normal JTAG access. The resistor-based 101 debug-mode rework option is lost.", "sourceIds": [ "UG470" ] }, { "id": "SPI_X1_BOOT", "severity": "minimum-parts-change", "endpoints": [ "U1.L14", "U1.M14" ], "summary": "Master SPI x1 boot removes R106/R107 and the optional DQ2/DQ3 paths. R101/R102 still hold flash WP# and RESET# high. Configuration is slower than quad SPI; the ASIC recording interface is unchanged. The programming image must explicitly use SPI x1.", "sourceIds": [ "UG470" ] } ], "nativeDesignChangedSincePreviousAudit": true, "removedFromPreviousAudit": [ "R106", "R107", "R112", "R113", "R12" ] }