# Power status and who owns the remaining work

27 September 2026 · smallest board: 33 × 36 mm · review, not a production release

**Selected boot simplification:** fixed SPI x1 removes R106/R107 and marks U1.L14/M14 NC; the flash WP#/RESET# pull-ups remain. The resulting design has **125 components, 752 numbered endpoints, 83 intentional NC and 19 reserved endpoints**. One-bit boot is slower than quad at the same clock; ASIC capture bandwidth is unchanged. See the [source review and boot constraints](../reports/SPIx1_Boot_Review.md).

**The power architecture and exact major parts are selected. Reliable power-up still needs final PCB verification and measurements on an assembled board.** Copper continuity, acceptable voltage drop, stable regulation and measured operation are separate checks. Use the latest integrated native audit for routing/ERC/DRC status; this page deliberately does not repeat changing route counts.

The current construction is **JLC12161H1-1080B**, twelve copper layers, planned nominal 1.6 mm ordering thickness and **1.59 mm ±10%** listed finished thickness. See the [physical proposal](../reports/Physical_Stackup_Proposal.md), [independent construction review](../reports/Twelve_Layer_Stackup_Review.md), and final hash-bound [physical application](../reports/Physical_Stackup_Application.json). The earlier eight-layer JLC08161H-3313 proposal is historical.

The custom J4 cable supplies a proposed 12 V input. Four TPS62135RGXR converters generate the FPGA core rail, 1.8 V auxiliary/configuration rail, 1.5 V ASIC-interface rail and 2.5 V reserved-link rail. The core converter is set near 1.025 V so that the FPGA receives approximately 1.0 V after distribution loss. This FPGA board does **not** automatically power the ASIC carrier. The XEM8310 is not, by itself, a defined 12 V source for J4.

R9 is selected as **12 mΩ, WSLP1206R0120FEA**, reducing core-feed loss while retaining the TI distributed-load isolation resistance. R122 stays 15 mΩ. The selected compact C20 is ETPE330M9GB; its smaller body does not by itself establish AMD decoupling-class equivalence or a stable mounted PDN. The [earlier DC review](../reports/Core_DC_Drop_Review.md) estimated about 11–21 mV of lower-rail margin in one 2 A / 85°C screen on the eight-layer intermediate geometry, before transient excursions. **That figure is historical, not a final twelve-layer margin.** The current construction has 30 µm power copper rather than 15.2 µm, so final feed/return geometry and spreading resistance require a matching calculation. No 2 A operating guarantee or 3 A qualification is established. R12's unused final power-good pull-up is removed in the approved integration change; U4.7 and U5.7 become intentional NC. The upstream power-good sequencing remains necessary.

| Remaining result | Owner | Evidence needed to close it |
|---|---|---|
| A consistent, electrically checked PCB | FPGA PCB designer | Final filled-board connectivity, ERC/DRC and schematic/BOM/PCB agreement; inspect supply and return paths and assembly clearances |
| Adequate power margin | FPGA PCB designer + firmware developer | Activity-based FPGA power estimate, effective capacitor/PDN assessment and load-step/startup/thermal checks; then measured rails at the FPGA |
| A usable power/programming fixture | System integration; Howard coordinates access | Protected supply, verified custom cable at both mating views, contact/cable current and temperature limits, and a 1.8 V-compatible JTAG adapter |
| An electrically and mechanically compatible carrier | Routing-board designer | Both connector contact maps, mating part/height/orientation, ground-blade connections, ASIC supplies and the external AC_IN source |
| A first recording bitstream | Jiaao / FPGA developer, with Gerald's ASIC details | SPI values, reset polarities/durations, safe inactive controls, actual clock/data timing, Vivado implementation and JTAG debug/readout integration |
| Proven startup and recording | Lab team; Howard coordinates | Unpowered checks, measured startup/current/temperature, JTAG identification, then known-pattern capture from one ASIC before eight |

**Howard's immediate coordination is small:** obtain the carrier's current schematic/contact map and Jiaao's current acquisition code/constraints. Gerald already supplied the nominal 1.5 V interface, analog AC_IN, SPI → resets → recording-clock order and falling-edge sampling. Do not resend those answered questions. The authorized working assumptions remain eight returned capture clocks, four outgoing board clocks and provisional digital IMP_TST; exact timing and safe states still need implementation evidence.

The first demonstration can store a short raw recording and inspect it through JTAG. The [capture engine](https://howardwhsrun.github.io/FPGA_4K/firmware/artix7/2026-09-26/raw_capture/README.md) passes synthetic simulation and XC7 synthesis, but it does not yet contain ASIC startup controls, JTAG readout transport, a complete bitstream or the XEM8310 streaming link. The full XEM link remains required for the eventual complete system.

Before any eventual manufacturing release, fabrication/assembly integration must obtain acceptance of J4's precision plated slots **and its short shell tabs recessed within the selected 1.59 mm board**, including soldering, inspection and retention, along with the mixed BGA/0402/mezzanine assembly. This is a process-acceptance requirement, not a demonstrated thickness mismatch; see the [connector thickness review](../reports/Connector_Thickness_And_Peg_Review.md). The mezzanine's Ø1.02 mm alignment holes match the drawing and have no opposite-side component overlap in the inspected intermediate layout; repeat that screen at the final placement. See the [qualification summary](../reports/Qualification_Summary.md) and [fabrication notes](../reports/Fabrication_Notes.md). **No order, supplier submission, bitstream or assembled-board electrical-operation evidence is claimed.**